#ifndef __TMIO_COMMON_H__
#define __TMIO_COMMON_H__
+#include <linux/bitops.h>
#define TMIO_SD_CMD 0x000 /* command */
#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
#define TMIO_SD_DMA_MODE 0x410
#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
+#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */
#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
#define TMIO_SD_DMA_CTL 0x414
#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
void __iomem *regbase;
unsigned int version;
u32 caps;
+ u32 read_poll_flag;
+ u32 idma_bus_width;
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
struct clk clk;
#endif
#if CONFIG_IS_ENABLED(RENESAS_SDHI)
+ unsigned int smpcmp;
u8 tap_set;
+ u8 tap_num;
u8 nrtaps;
+ bool needs_adjust_hs400;
+ bool adjust_hs400_enable;
+ u8 adjust_hs400_offset;
+ u8 adjust_hs400_calibrate;
+ u8 hs400_bad_tap;
+ const u8 *adjust_hs400_calib_table;
+ u32 quirks;
#endif
ulong (*clk_get_rate)(struct tmio_sd_priv *);
};