// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_MMC
+
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
+#include <asm/bitops.h>
#include <asm/cache.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/libfdt.h>
#include <mmc.h>
#include <reset.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/iopoll.h>
+#include <power/regulator.h>
#include <watchdog.h>
struct stm32_sdmmc2_plat {
struct mmc_config cfg;
struct mmc mmc;
-};
-
-struct stm32_sdmmc2_priv {
fdt_addr_t base;
struct clk clk;
struct reset_ctl reset_ctl;
struct gpio_desc cd_gpio;
u32 clk_reg_msk;
u32 pwr_reg_msk;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ bool vqmmc_enabled;
+#endif
};
struct stm32_sdmmc2_ctx {
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
#define SDMMC_BUSYD0END_TIMEOUT_US 2000000
-static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
+static void stm32_sdmmc2_start_data(struct udevice *dev,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
u32 data_ctrl, idmabase0;
/* Configure the SDMMC DPSM (Data Path State Machine) */
}
/* Set the SDMMC DataLength value */
- writel(ctx->data_length, priv->base + SDMMC_DLEN);
+ writel(ctx->data_length, plat->base + SDMMC_DLEN);
/* Write to SDMMC DCTRL */
- writel(data_ctrl, priv->base + SDMMC_DCTRL);
+ writel(data_ctrl, plat->base + SDMMC_DCTRL);
/* Cache align */
ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
flush_dcache_range(ctx->cache_start, ctx->cache_end);
/* Enable internal DMA */
- writel(idmabase0, priv->base + SDMMC_IDMABASE0);
- writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
+ writel(idmabase0, plat->base + SDMMC_IDMABASE0);
+ writel(SDMMC_IDMACTRL_IDMAEN, plat->base + SDMMC_IDMACTRL);
}
-static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
+static void stm32_sdmmc2_start_cmd(struct udevice *dev,
struct mmc_cmd *cmd, u32 cmd_param,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
u32 timeout = 0;
- if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
- writel(0, priv->base + SDMMC_CMD);
+ if (readl(plat->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
+ writel(0, plat->base + SDMMC_CMD);
cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (ctx->data_length) {
timeout = SDMMC_CMD_TIMEOUT;
} else {
- writel(0, priv->base + SDMMC_DCTRL);
+ writel(0, plat->base + SDMMC_DCTRL);
if (cmd->resp_type & MMC_RSP_BUSY)
timeout = SDMMC_CMD_TIMEOUT;
}
/* Set the SDMMC Data TimeOut value */
- writel(timeout, priv->base + SDMMC_DTIMER);
+ writel(timeout, plat->base + SDMMC_DTIMER);
/* Clear flags */
- writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
+ writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR);
/* Set SDMMC argument value */
- writel(cmd->cmdarg, priv->base + SDMMC_ARG);
+ writel(cmd->cmdarg, plat->base + SDMMC_ARG);
/* Set SDMMC command parameters */
- writel(cmd_param, priv->base + SDMMC_CMD);
+ writel(cmd_param, plat->base + SDMMC_CMD);
}
-static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
+static int stm32_sdmmc2_end_cmd(struct udevice *dev,
struct mmc_cmd *cmd,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
u32 mask = SDMMC_STA_CTIMEOUT;
u32 status;
int ret;
}
/* Polling status register */
- ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
+ ret = readl_poll_timeout(plat->base + SDMMC_STA, status, status & mask,
10000);
if (ret < 0) {
- debug("%s: timeout reading SDMMC_STA register\n", __func__);
+ dev_dbg(dev, "timeout reading SDMMC_STA register\n");
ctx->dpsm_abort = true;
return ret;
}
/* Check status */
if (status & SDMMC_STA_CTIMEOUT) {
- debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
- debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EILSEQ;
}
if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
- cmd->response[0] = readl(priv->base + SDMMC_RESP1);
+ cmd->response[0] = readl(plat->base + SDMMC_RESP1);
if (cmd->resp_type & MMC_RSP_136) {
- cmd->response[1] = readl(priv->base + SDMMC_RESP2);
- cmd->response[2] = readl(priv->base + SDMMC_RESP3);
- cmd->response[3] = readl(priv->base + SDMMC_RESP4);
+ cmd->response[1] = readl(plat->base + SDMMC_RESP2);
+ cmd->response[2] = readl(plat->base + SDMMC_RESP3);
+ cmd->response[3] = readl(plat->base + SDMMC_RESP4);
}
/* Wait for BUSYD0END flag if busy status is detected */
mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
/* Polling status register */
- ret = readl_poll_timeout(priv->base + SDMMC_STA,
+ ret = readl_poll_timeout(plat->base + SDMMC_STA,
status, status & mask,
SDMMC_BUSYD0END_TIMEOUT_US);
if (ret < 0) {
- debug("%s: timeout reading SDMMC_STA\n",
- __func__);
+ dev_dbg(dev, "timeout reading SDMMC_STA\n");
ctx->dpsm_abort = true;
return ret;
}
if (status & SDMMC_STA_DTIMEOUT) {
- debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
- __func__, status);
+ dev_dbg(dev,
+ "error SDMMC_STA_DTIMEOUT (0x%x)\n",
+ status);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
return 0;
}
-static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
+static int stm32_sdmmc2_end_data(struct udevice *dev,
struct mmc_cmd *cmd,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
u32 status;
else
mask |= SDMMC_STA_TXUNDERR;
- status = readl(priv->base + SDMMC_STA);
+ status = readl(plat->base + SDMMC_STA);
while (!(status & mask))
- status = readl(priv->base + SDMMC_STA);
+ status = readl(plat->base + SDMMC_STA);
/*
* Need invalidate the dcache again to avoid any
invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
if (status & SDMMC_STA_DCRCFAIL) {
- debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
- if (readl(priv->base + SDMMC_DCOUNT))
+ dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
+ if (readl(plat->base + SDMMC_DCOUNT))
ctx->dpsm_abort = true;
return -EILSEQ;
}
if (status & SDMMC_STA_DTIMEOUT) {
- debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
if (status & SDMMC_STA_TXUNDERR) {
- debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
if (status & SDMMC_STA_RXOVERR) {
- debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
if (status & SDMMC_STA_IDMATE) {
- debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
struct stm32_sdmmc2_ctx ctx;
u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
int ret, retry = 3;
- WATCHDOG_RESET();
+ schedule();
retry_cmd:
ctx.data_length = 0;
if (data) {
ctx.data_length = data->blocks * data->blocksize;
- stm32_sdmmc2_start_data(priv, data, &ctx);
+ stm32_sdmmc2_start_data(dev, data, &ctx);
}
- stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
+ stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
- debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
- __func__, cmd->cmdidx,
- data ? ctx.data_length : 0, (unsigned int)data);
+ dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
+ cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
- ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
+ ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
if (data && !ret)
- ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
+ ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
/* Clear flags */
- writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
+ writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR);
if (data)
- writel(0x0, priv->base + SDMMC_IDMACTRL);
+ writel(0x0, plat->base + SDMMC_IDMACTRL);
/*
* To stop Data Path State Machine, a stop_transmission command
stop_cmd.cmdarg = 0;
stop_cmd.resp_type = MMC_RSP_R1b;
- debug("%s: send STOP command to abort dpsm treatments\n",
- __func__);
+ dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
ctx.data_length = 0;
- stm32_sdmmc2_start_cmd(priv, &stop_cmd,
+ stm32_sdmmc2_start_cmd(dev, &stop_cmd,
SDMMC_CMD_CMDSTOP, &ctx);
- stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
+ stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
- writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
+ writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR);
}
if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
- printf("%s: cmd %d failed, retrying ...\n",
- __func__, cmd->cmdidx);
+ dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
retry--;
goto retry_cmd;
}
- debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
+ dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
return ret;
}
* This will reset the SDMMC to the reset state and the CPSM and DPSM
* to the Idle state. SDMMC is disabled, Signals Hiz.
*/
-static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
+static void stm32_sdmmc2_reset(struct stm32_sdmmc2_plat *plat)
{
- /* Reset */
- reset_assert(&priv->reset_ctl);
- udelay(2);
- reset_deassert(&priv->reset_ctl);
+ if (reset_valid(&plat->reset_ctl)) {
+ /* Reset */
+ reset_assert(&plat->reset_ctl);
+ udelay(2);
+ reset_deassert(&plat->reset_ctl);
+ }
/* init the needed SDMMC register after reset */
- writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
+ writel(plat->pwr_reg_msk, plat->base + SDMMC_POWER);
}
/*
* SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
* supplied through the signal lines.
*/
-static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
+static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_plat *plat)
{
- if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
+ if ((readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
SDMMC_POWER_PWRCTRL_CYCLE)
return;
- stm32_sdmmc2_reset(priv);
+ stm32_sdmmc2_reset(plat);
}
/*
* Reset => Power-Cycle => Power-Off => Power
* PWRCTRL=10 PWCTRL=00 PWCTRL=11
*/
-static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
+static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_plat *plat)
{
u32 pwrctrl =
- readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
+ readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
return;
* it is the reset state here = the only managed by the driver
*/
if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
- writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
- priv->base + SDMMC_POWER);
+ writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk,
+ plat->base + SDMMC_POWER);
}
/*
* the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
* switch to Power-Off state: SDMCC disable, signals drive 1
*/
- writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
- priv->base + SDMMC_POWER);
+ writel(SDMMC_POWER_PWRCTRL_OFF | plat->pwr_reg_msk,
+ plat->base + SDMMC_POWER);
/* After the 1ms delay set the SDMMC to power-on */
mdelay(1);
- writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
- priv->base + SDMMC_POWER);
+ writel(SDMMC_POWER_PWRCTRL_ON | plat->pwr_reg_msk,
+ plat->base + SDMMC_POWER);
/* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (plat->mmc.vqmmc_supply && !plat->vqmmc_enabled) {
+ if (regulator_set_enable_if_allowed(plat->mmc.vqmmc_supply, true))
+ dev_dbg(plat->mmc.dev, "failed to enable vqmmc-supply\n");
+ else
+ plat->vqmmc_enabled = true;
+ }
+#endif
}
#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
static int stm32_sdmmc2_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
- struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
u32 desired = mmc->clock;
- u32 sys_clock = clk_get_rate(&priv->clk);
+ u32 sys_clock = clk_get_rate(&plat->clk);
u32 clk = 0;
- debug("%s: bus_with = %d, clock = %d\n", __func__,
- mmc->bus_width, mmc->clock);
+ dev_dbg(dev, "bus_with = %d, clock = %d\n",
+ mmc->bus_width, mmc->clock);
if (mmc->clk_disable)
- stm32_sdmmc2_pwrcycle(priv);
+ stm32_sdmmc2_pwrcycle(plat);
else
- stm32_sdmmc2_pwron(priv);
+ stm32_sdmmc2_pwron(plat);
/*
* clk_div = 0 => command and data generated on SDMMCCLK falling edge
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
* SDMMCCLK falling edge
*/
- if (desired && ((sys_clock > desired) ||
- IS_RISING_EDGE(priv->clk_reg_msk))) {
+ if (desired && (sys_clock > desired || mmc->ddr_mode ||
+ IS_RISING_EDGE(plat->clk_reg_msk))) {
clk = DIV_ROUND_UP(sys_clock, 2 * desired);
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
clk = SDMMC_CLKCR_CLKDIV_MAX;
}
+ if (mmc->ddr_mode)
+ clk |= SDMMC_CLKCR_DDR;
+
if (mmc->bus_width == 4)
clk |= SDMMC_CLKCR_WIDBUS_4;
if (mmc->bus_width == 8)
clk |= SDMMC_CLKCR_WIDBUS_8;
- writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
- priv->base + SDMMC_CLKCR);
+ writel(clk | plat->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
+ plat->base + SDMMC_CLKCR);
return 0;
}
static int stm32_sdmmc2_getcd(struct udevice *dev)
{
- struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
- debug("stm32_sdmmc2_getcd called\n");
+ dev_dbg(dev, "%s called\n", __func__);
- if (dm_gpio_is_valid(&priv->cd_gpio))
- return dm_gpio_get_value(&priv->cd_gpio);
+ if (dm_gpio_is_valid(&plat->cd_gpio))
+ return dm_gpio_get_value(&plat->cd_gpio);
return 1;
}
static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
{
- struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
- writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
- priv->base + SDMMC_POWER);
+ writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk,
+ plat->base + SDMMC_POWER);
return 0;
}
.host_power_cycle = stm32_sdmmc2_host_power_cycle,
};
-static int stm32_sdmmc2_probe(struct udevice *dev)
+static int stm32_sdmmc2_of_to_plat(struct udevice *dev)
{
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
- struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
int ret;
- priv->base = dev_read_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
+ plat->base = dev_read_addr(dev);
+ if (plat->base == FDT_ADDR_T_NONE)
return -EINVAL;
if (dev_read_bool(dev, "st,neg-edge"))
- priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
+ plat->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
if (dev_read_bool(dev, "st,sig-dir"))
- priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
+ plat->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
if (dev_read_bool(dev, "st,use-ckin"))
- priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
+ plat->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
- ret = clk_get_by_index(dev, 0, &priv->clk);
+ cfg->f_min = 400000;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ cfg->name = "STM32 SD/MMC";
+ cfg->host_caps = 0;
+ cfg->f_max = 52000000;
+ ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
- ret = clk_enable(&priv->clk);
+ cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES);
+
+ ret = clk_get_by_index(dev, 0, &plat->clk);
if (ret)
- goto clk_free;
+ return ret;
- ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
+ ret = reset_get_by_index(dev, 0, &plat->reset_ctl);
if (ret)
- goto clk_disable;
+ dev_dbg(dev, "No reset provided\n");
- gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio,
GPIOD_IS_IN);
- cfg->f_min = 400000;
- cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
- cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- cfg->name = "STM32 SD/MMC";
+ return 0;
+}
- cfg->host_caps = 0;
- if (cfg->f_max > 25000000)
- cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-
- switch (dev_read_u32_default(dev, "bus-width", 1)) {
- case 8:
- cfg->host_caps |= MMC_MODE_8BIT;
- /* fall through */
- case 4:
- cfg->host_caps |= MMC_MODE_4BIT;
- break;
- case 1:
- break;
- default:
- pr_err("invalid \"bus-width\" property, force to 1\n");
+static int stm32_sdmmc2_probe_level_translator(struct udevice *dev)
+{
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
+ struct gpio_desc cmd_gpio;
+ struct gpio_desc ck_gpio;
+ struct gpio_desc ckin_gpio;
+ int clk_hi, clk_lo, ret;
+
+ ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret)
+ goto exit_cmd;
+
+ ret = gpio_request_by_name(dev, "st,ck-gpios", 0, &ck_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret)
+ goto exit_ck;
+
+ ret = gpio_request_by_name(dev, "st,ckin-gpios", 0, &ckin_gpio,
+ GPIOD_IS_IN);
+ if (ret)
+ goto exit_ckin;
+
+ /* All GPIOs are valid, test whether level translator works */
+
+ /* Sample CKIN */
+ clk_hi = !!dm_gpio_get_value(&ckin_gpio);
+
+ /* Set CK low */
+ dm_gpio_set_value(&ck_gpio, 0);
+
+ /* Sample CKIN */
+ clk_lo = !!dm_gpio_get_value(&ckin_gpio);
+
+ /* Tristate all */
+ dm_gpio_set_dir_flags(&cmd_gpio, GPIOD_IS_IN);
+ dm_gpio_set_dir_flags(&ck_gpio, GPIOD_IS_IN);
+
+ /* Level translator is present if CK signal is propagated to CKIN */
+ if (!clk_hi || clk_lo)
+ plat->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN;
+
+ dm_gpio_free(dev, &ckin_gpio);
+
+exit_ckin:
+ dm_gpio_free(dev, &ck_gpio);
+exit_ck:
+ dm_gpio_free(dev, &cmd_gpio);
+exit_cmd:
+ pinctrl_select_state(dev, "default");
+
+ return 0;
+}
+
+static int stm32_sdmmc2_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
+ int ret;
+
+ ret = clk_enable(&plat->clk);
+ if (ret) {
+ clk_free(&plat->clk);
+ return ret;
}
upriv->mmc = &plat->mmc;
- /* SDMMC init */
- stm32_sdmmc2_reset(priv);
- return 0;
+ if (plat->clk_reg_msk & SDMMC_CLKCR_SELCLKRX_CKIN)
+ stm32_sdmmc2_probe_level_translator(dev);
-clk_disable:
- clk_disable(&priv->clk);
-clk_free:
- clk_free(&priv->clk);
+ /* SDMMC init */
+ stm32_sdmmc2_reset(plat);
- return ret;
+ return 0;
}
-static int stm32_sdmmc_bind(struct udevice *dev)
+static int stm32_sdmmc2_bind(struct udevice *dev)
{
- struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.of_match = stm32_sdmmc2_ids,
.ops = &stm32_sdmmc2_ops,
.probe = stm32_sdmmc2_probe,
- .bind = stm32_sdmmc_bind,
- .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
- .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
+ .bind = stm32_sdmmc2_bind,
+ .of_to_plat = stm32_sdmmc2_of_to_plat,
+ .plat_auto = sizeof(struct stm32_sdmmc2_plat),
};
projects / platform / kernel / u-boot.git / blobdiff