#include <common.h>
#include <clk.h>
+#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/bitops.h>
+#include <asm/cache.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/libfdt.h>
#include <mmc.h>
#include <reset.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/iopoll.h>
+#include <watchdog.h>
struct stm32_sdmmc2_plat {
struct mmc_config cfg;
u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
int ret, retry = 3;
+ WATCHDOG_RESET();
+
retry_cmd:
ctx.data_length = 0;
ctx.dpsm_abort = false;
return;
stm32_sdmmc2_reset(priv);
- writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
- priv->base + SDMMC_POWER);
}
/*
return 1;
}
+static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
+{
+ struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+
+ writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
+ priv->base + SDMMC_POWER);
+
+ return 0;
+}
+
static const struct dm_mmc_ops stm32_sdmmc2_ops = {
.send_cmd = stm32_sdmmc2_send_cmd,
.set_ios = stm32_sdmmc2_set_ios,
.get_cd = stm32_sdmmc2_getcd,
+ .host_power_cycle = stm32_sdmmc2_host_power_cycle,
};
static int stm32_sdmmc2_probe(struct udevice *dev)
cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- cfg->name = "STM32 SDMMC2";
+ cfg->name = "STM32 SD/MMC";
cfg->host_caps = 0;
if (cfg->f_max > 25000000)