Merge tag 'v2021.01-rc5' into next

[platform/kernel/u-boot.git] / drivers / mmc / stm32_sdmmc2.c

diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 32434a4..3246f6b 100644 (file)
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -1,13 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  */
 
 #include <common.h>
 #include <clk.h>
+#include <cpu_func.h>
 #include <dm.h>
 #include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/bitops.h>
+#include <asm/cache.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 #include <linux/libfdt.h>
 #include <mmc.h>
 #include <reset.h>
@@ -524,8 +531,6 @@ static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
                return;
 
        stm32_sdmmc2_reset(priv);
-       writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
-              priv->base + SDMMC_POWER);
 }
 
 /*
@@ -619,16 +624,27 @@ static int stm32_sdmmc2_getcd(struct udevice *dev)
        return 1;
 }
 
+static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
+{
+       struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
+
+       writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
+              priv->base + SDMMC_POWER);
+
+       return 0;
+}
+
 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
        .send_cmd = stm32_sdmmc2_send_cmd,
        .set_ios = stm32_sdmmc2_set_ios,
        .get_cd = stm32_sdmmc2_getcd,
+       .host_power_cycle = stm32_sdmmc2_host_power_cycle,
 };
 
 static int stm32_sdmmc2_probe(struct udevice *dev)
 {
        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-       struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
+       struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
        struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
        struct mmc_config *cfg = &plat->cfg;
        int ret;
@@ -660,27 +676,13 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
                             GPIOD_IS_IN);
 
        cfg->f_min = 400000;
-       cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
        cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
-       cfg->name = "STM32 SDMMC2";
+       cfg->name = "STM32 SD/MMC";
 
        cfg->host_caps = 0;
-       if (cfg->f_max > 25000000)
-               cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-
-       switch (dev_read_u32_default(dev, "bus-width", 1)) {
-       case 8:
-               cfg->host_caps |= MMC_MODE_8BIT;
-               /* fall through */
-       case 4:
-               cfg->host_caps |= MMC_MODE_4BIT;
-               break;
-       case 1:
-               break;
-       default:
-               pr_err("invalid \"bus-width\" property, force to 1\n");
-       }
+       cfg->f_max = 52000000;
+       mmc_of_parse(dev, cfg);
 
        upriv->mmc = &plat->mmc;
 
@@ -698,7 +700,7 @@ clk_free:
 
 static int stm32_sdmmc_bind(struct udevice *dev)
 {
-       struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
+       struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
 
        return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }
@@ -715,6 +717,6 @@ U_BOOT_DRIVER(stm32_sdmmc2) = {
        .ops = &stm32_sdmmc2_ops,
        .probe = stm32_sdmmc2_probe,
        .bind = stm32_sdmmc_bind,
-       .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
-       .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
+       .priv_auto      = sizeof(struct stm32_sdmmc2_priv),
+       .plat_auto      = sizeof(struct stm32_sdmmc2_plat),
 };