Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into...

[platform/kernel/u-boot.git] / drivers / mmc / socfpga_dw_mmc.c

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 739c162..892222d 100644 (file)
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <log.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/system_manager.h>
 #include <clk.h>
@@ -11,6 +12,7 @@
 #include <dwmmc.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <dm/device_compat.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
 #include <malloc.h>
@@ -18,11 +20,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-               (void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
-               (void *)SOCFPGA_SYSMGR_ADDRESS;
-
 struct socfpga_dwmci_plat {
        struct mmc_config cfg;
        struct mmc mmc;
@@ -56,19 +53,19 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
                         ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
        /* Disable SDMMC clock. */
-       clrbits_le32(&clock_manager_base->per_pll.en,
-               CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+                    CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
        debug("%s: drvsel %d smplsel %d\n", __func__,
              priv->drvsel, priv->smplsel);
-       writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
+       writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
        debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
-               readl(&system_manager_base->sdmmcgrp_ctrl));
+               readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
 
        /* Enable SDMMC clock */
-       setbits_le32(&clock_manager_base->per_pll.en,
-               CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+                    CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)