Merge tag 'efi-2022-01-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

[platform/kernel/u-boot.git] / drivers / mmc / mv_sdhci.c

diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index de4ae0a..336ebf1 100644 (file)
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -4,10 +4,14 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <malloc.h>
 #include <sdhci.h>
+#include <asm/global_data.h>
 #include <linux/mbus.h>
 
+#define MVSDH_NAME "mv_sdh"
+
 #define SDHCI_WINDOW_CTRL(win)         (0x4080 + ((win) << 4))
 #define SDHCI_WINDOW_BASE(win)         (0x4084 + ((win) << 4))
 
@@ -36,34 +40,12 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
        }
 }
 
+#ifndef CONFIG_DM_MMC
+
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 static struct sdhci_ops mv_ops;
-
-#if defined(CONFIG_SHEEVA_88SV331xV5)
-#define SD_CE_ATA_2    0xEA
-#define  MMC_CARD      0x1000
-#define  MMC_WIDTH     0x0100
-static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
-{
-       struct mmc *mmc = host->mmc;
-       u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
-
-       if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
-               if (mmc->bus_width == 8)
-                       writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
-               else
-                       writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
-       }
-
-       writeb(val, host->ioaddr + reg);
-}
-
-#else
-#define mv_sdhci_writeb        NULL
-#endif /* CONFIG_SHEEVA_88SV331xV5 */
 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 
-static char *MVSDH_NAME = "mv_sdh";
 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
 {
        struct sdhci_host *host = NULL;
@@ -79,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
        host->max_clk = max_clk;
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
        memset(&mv_ops, 0, sizeof(struct sdhci_ops));
-       mv_ops.write_b = mv_sdhci_writeb;
        host->ops = &mv_ops;
 #endif
 
@@ -90,3 +71,68 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
 
        return add_sdhci(host, 0, min_clk);
 }
+
+#else
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mv_sdhci_plat {
+       struct mmc_config cfg;
+       struct mmc mmc;
+};
+
+static int mv_sdhci_probe(struct udevice *dev)
+{
+       struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+       struct mv_sdhci_plat *plat = dev_get_plat(dev);
+       struct sdhci_host *host = dev_get_priv(dev);
+       int ret;
+
+       host->name = MVSDH_NAME;
+       host->ioaddr = dev_read_addr_ptr(dev);
+       host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
+       host->mmc = &plat->mmc;
+       host->mmc->dev = dev;
+       host->mmc->priv = host;
+
+       ret = mmc_of_parse(dev, &plat->cfg);
+       if (ret)
+               return ret;
+
+       ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+       if (ret)
+               return ret;
+
+       if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
+               /* Configure SDHCI MBUS mbus bridge windows */
+               sdhci_mvebu_mbus_config(host->ioaddr);
+       }
+
+       upriv->mmc = host->mmc;
+
+       return sdhci_probe(dev);
+}
+
+static int mv_sdhci_bind(struct udevice *dev)
+{
+       struct mv_sdhci_plat *plat = dev_get_plat(dev);
+
+       return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id mv_sdhci_ids[] = {
+       { .compatible = "marvell,armada-380-sdhci" },
+       { }
+};
+
+U_BOOT_DRIVER(mv_sdhci_drv) = {
+       .name           = MVSDH_NAME,
+       .id             = UCLASS_MMC,
+       .of_match       = mv_sdhci_ids,
+       .bind           = mv_sdhci_bind,
+       .probe          = mv_sdhci_probe,
+       .ops            = &sdhci_ops,
+       .priv_auto      = sizeof(struct sdhci_host),
+       .plat_auto      = sizeof(struct mv_sdhci_plat),
+};
+#endif /* CONFIG_DM_MMC */