#include <malloc.h>
#include <mapmem.h>
#include <stdbool.h>
-#include <watchdog.h>
#include <asm/gpio.h>
+#include <dm/device_compat.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <linux/io.h>
blocks = data->blocks;
writel(CMD_INTS_MASK, &host->base->msdc_int);
+ writel(DATA_INTS_MASK, &host->base->msdc_int);
writel(blocks, &host->base->sdc_blk_num);
writel(cmd->cmdarg, &host->base->sdc_arg);
writel(rawcmd, &host->base->sdc_cmd);
u32 size;
int ret;
- WATCHDOG_RESET();
-
if (data->flags == MMC_DATA_WRITE)
host->last_data_write = 1;
- writel(DATA_INTS_MASK, &host->base->msdc_int);
-
size = data->blocks * data->blocksize;
if (data->flags == MMC_DATA_WRITE)
writel(val, &host->base->sdc_cfg);
}
-static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
+static void msdc_set_mclk(struct udevice *dev,
+ struct msdc_host *host, enum bus_mode timing, u32 hz)
{
u32 mode;
u32 div;
clock = mmc->cfg->f_min;
if (host->mclk != clock || host->timing != mmc->selected_mode)
- msdc_set_mclk(host, mmc->selected_mode, clock);
+ msdc_set_mclk(dev, host, mmc->selected_mode, clock);
return 0;
}
return PAD_DELAY_MAX - start_bit;
}
-static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
+static struct msdc_delay_phase get_best_delay(struct udevice *dev,
+ struct msdc_host *host, u32 delay)
{
int start = 0, len = 0;
int start_final = 0, len_final = 0;
}
}
- final_cmd_delay = get_best_delay(host, cmd_delay);
+ final_cmd_delay = get_best_delay(dev, host, cmd_delay);
clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
final_cmd_delay.final_phase <<
PAD_CMD_TUNE_RX_DLY3_S);
}
}
- final_rise_delay = get_best_delay(host, rise_delay);
+ final_rise_delay = get_best_delay(dev, host, rise_delay);
/* if rising edge has enough margin, do not scan falling edge */
if (final_rise_delay.maxlen >= 12 ||
(final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
}
}
- final_fall_delay = get_best_delay(host, fall_delay);
+ final_fall_delay = get_best_delay(dev, host, fall_delay);
skip_fall:
final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
internal_delay |= (1 << i);
}
- dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
+ dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
- internal_delay_phase = get_best_delay(host, internal_delay);
+ internal_delay_phase = get_best_delay(dev, host, internal_delay);
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
internal_delay_phase.final_phase <<
MSDC_PAD_TUNE_CMDRRDLY_S);
skip_internal:
- dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
}
}
- final_rise_delay = get_best_delay(host, rise_delay);
+ final_rise_delay = get_best_delay(dev, host, rise_delay);
if (final_rise_delay.maxlen >= 12 ||
(final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
goto skip_fall;
}
}
- final_fall_delay = get_best_delay(host, fall_delay);
+ final_fall_delay = get_best_delay(dev, host, fall_delay);
skip_fall:
final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
host->hs200_write_int_delay <<
MSDC_PAD_TUNE_DATWRDLY_S);
- dev_err(dev, "Final data pad delay: %x\n", final_delay);
+ dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
rise_delay |= (1 << i);
}
- final_rise_delay = get_best_delay(host, rise_delay);
+ final_rise_delay = get_best_delay(dev, host, rise_delay);
if (final_rise_delay.maxlen >= 12 ||
(final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
goto skip_fall;
fall_delay |= (1 << i);
}
- final_fall_delay = get_best_delay(host, fall_delay);
+ final_fall_delay = get_best_delay(dev, host, fall_delay);
skip_fall:
final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
.enhance_rx = false
};
+static const struct msdc_compatible mt7622_compat = {
+ .clk_div_bits = 12,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct msdc_compatible mt7623_compat = {
.clk_div_bits = 12,
.sclk_cycle_shift = 20,
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
+ { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
{ .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
.bind = msdc_drv_bind,
.probe = msdc_drv_probe,
.ops = &msdc_ops,
- .platdata_auto_alloc_size = sizeof(struct msdc_plat),
- .priv_auto_alloc_size = sizeof(struct msdc_host),
+ .platdata_auto = sizeof(struct msdc_plat),
+ .priv_auto = sizeof(struct msdc_host),
};