+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Carlo Caione <carlo@caione.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
+#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <pwrseq.h>
#include <mmc.h>
#include <asm/io.h>
-#include <asm/arch/sd_emmc.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
#include <linux/log2.h>
+#include "meson_gx_mmc.h"
+
+bool meson_gx_mmc_is_compatible(struct udevice *dev,
+ enum meson_gx_mmc_compatible family)
+{
+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
+
+ return compat == family;
+}
static inline void *get_regbase(const struct mmc *mmc)
{
uint32_t meson_mmc_clk = 0;
unsigned int clk, clk_src, clk_div;
+ if (!mmc->clock)
+ return;
+
+ /* TOFIX This should use the proper clock taken from DT */
+
/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
if (mmc->clock > 16000000) {
clk = SD_EMMC_CLKSRC_DIV2;
}
clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
+ /*
+ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
+ * If CLK_CO_PHASE_270 is used, it's more stable than other.
+ * Other SoCs use CLK_CO_PHASE_180 by default.
+ * It needs to find what is a proper value about each SoCs.
+ */
+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
+ meson_mmc_clk |= CLK_CO_PHASE_270;
+ else
+ meson_mmc_clk |= CLK_CO_PHASE_180;
/* 180 phase tx clock */
meson_mmc_clk |= CLK_TX_PHASE_000;
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
struct mmc_config *cfg = &pdata->cfg;
+ struct clk_bulk clocks;
uint32_t val;
+ int ret;
+
+#ifdef CONFIG_PWRSEQ
+ struct udevice *pwr_dev;
+#endif
+
+ /* Enable the clocks feeding the MMC controller */
+ ret = clk_get_bulk(dev, &clocks);
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(&clocks);
+ if (ret)
+ return ret;
cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
MMC_VDD_31_32 | MMC_VDD_165_195;
mmc->priv = pdata;
upriv->mmc = mmc;
- mmc_set_clock(mmc, cfg->f_min);
+ mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
+
+#ifdef CONFIG_PWRSEQ
+ /* Enable power if needed */
+ ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
+ &pwr_dev);
+ if (!ret) {
+ ret = pwrseq_set_power(pwr_dev, true);
+ if (ret)
+ return ret;
+ }
+#endif
/* reset all status bits */
meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
}
static const struct udevice_id meson_mmc_match[] = {
- { .compatible = "amlogic,meson-gx-mmc" },
+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
{ /* sentinel */ }
};
.ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
};
+
+#ifdef CONFIG_PWRSEQ
+static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
+{
+ struct gpio_desc reset;
+ int ret;
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
+ if (ret)
+ return ret;
+ dm_gpio_set_value(&reset, 1);
+ udelay(1);
+ dm_gpio_set_value(&reset, 0);
+ udelay(200);
+
+ return 0;
+}
+
+static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
+ .set_power = meson_mmc_pwrseq_set_power,
+};
+
+static const struct udevice_id meson_mmc_pwrseq_ids[] = {
+ { .compatible = "mmc-pwrseq-emmc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
+ .name = "mmc_pwrseq_emmc",
+ .id = UCLASS_PWRSEQ,
+ .of_match = meson_mmc_pwrseq_ids,
+ .ops = &meson_mmc_pwrseq_ops,
+};
+#endif