mmc: meson-mx-sdhc: Fix initialization frozen issue

[platform/kernel/linux-rpi.git] / drivers / mmc / host / meson-mx-sdhc-mmc.c

diff --git a/drivers/mmc/host/meson-mx-sdhc-mmc.c b/drivers/mmc/host/meson-mx-sdhc-mmc.c
index 528ec81..1ed9731 100644 (file)
--- a/drivers/mmc/host/meson-mx-sdhc-mmc.c
+++ b/drivers/mmc/host/meson-mx-sdhc-mmc.c
@@ -269,7 +269,7 @@ static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
 static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
 {
        struct meson_mx_sdhc_host *host = mmc_priv(mmc);
-       u32 rx_clk_phase;
+       u32 val, rx_clk_phase;
        int ret;
 
        meson_mx_sdhc_disable_clks(mmc);
@@ -290,27 +290,11 @@ static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
                mmc->actual_clock = clk_get_rate(host->sd_clk);
 
                /*
-                * according to Amlogic the following latching points are
-                * selected with empirical values, there is no (known) formula
-                * to calculate these.
+                * Phase 90 should work in most cases. For data transmission,
+                * meson_mx_sdhc_execute_tuning() will find a accurate value
                 */
-               if (mmc->actual_clock > 100000000) {
-                       rx_clk_phase = 1;
-               } else if (mmc->actual_clock > 45000000) {
-                       if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
-                               rx_clk_phase = 15;
-                       else
-                               rx_clk_phase = 11;
-               } else if (mmc->actual_clock >= 25000000) {
-                       rx_clk_phase = 15;
-               } else if (mmc->actual_clock > 5000000) {
-                       rx_clk_phase = 23;
-               } else if (mmc->actual_clock > 1000000) {
-                       rx_clk_phase = 55;
-               } else {
-                       rx_clk_phase = 1061;
-               }
-
+               regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
+               rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4;
                regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
                                   MESON_SDHC_CLK2_RX_CLK_PHASE,
                                   FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,