config SPL_MMC_HS400_SUPPORT
bool "enable HS400 support in SPL"
+ select SPL_MMC_HS200_SUPPORT
help
The HS400 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
The HS200 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
-
config SPL_MMC_HS200_SUPPORT
bool "enable HS200 support in SPL"
help
This enables support for the ADMA (Advanced DMA) defined
in the SD Host Controller Standard Specification Version 3.00 in SPL.
+config MMC_SDHCI_ASPEED
+ bool "Aspeed SDHCI controller"
+ depends on ARCH_ASPEED
+ depends on DM_MMC
+ depends on MMC_SDHCI
+ help
+ Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
+ SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
+ specifications. On the AST2600, the device is also compatible with
+ MMC 5.1 and eMMC 3.0.
+
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
If unsure, say N.
-config MMC_SDHCI_K3_ARASAN
- bool "Arasan SDHCI controller for TI's K3 based SoCs"
+config MMC_SDHCI_AM654
+ bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
+ depends on REGMAP
help
- Support for Arasan SDHCI host controller on Texas Instruments'
- K3 family based SoC platforms
+ Support for Secure Digital Host Controller Interface (SDHCI)
+ controllers present on TI's AM654 SOCs.
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
If unsure, say N.
+config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
+ bool "Disable external clock loopback"
+ depends on MMC_SDHCI_TEGRA && TEGRA124
+ help
+ Disable the external clock loopback and use the internal one on SDMMC3
+ as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+ being set to 0xfffd according to the TRM.
+
+ TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
+ approach once proper kernel integration made it mainline.
+
config MMC_SDHCI_ZYNQ
bool "Arasan SDHCI controller support"
depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
help
Set the minimum frequency of the controller.
+config ZYNQ_HISPD_BROKEN
+ bool "High speed broken for Zynq SDHCI controller"
+ depends on MMC_SDHCI_ZYNQ
+ help
+ Set if high speed mode is broken.
+
config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
endif
-config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
- bool "Disable external clock loopback"
- depends on MMC_SDHCI_TEGRA && TEGRA124
- help
- Disable the external clock loopback and use the internal one on SDMMC3
- as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
- being set to 0xfffd according to the TRM.
-
- TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
- approach once proper kernel integration made it mainline.
-
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
+ select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
+config FSL_ESDHC_USE_PERIPHERAL_CLK
+ bool "enable ESDHC peripheral clock support"
+ depends on FSL_ESDHC
+ help
+ eSDHC supports two reference clocks (platform clock and peripheral clock).
+ Peripheral clock which could provide higher clock frequency is required to
+ be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
+
config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help
This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
+config FSL_USDHC
+ bool "Freescale/NXP i.MX uSDHC controller support"
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB
+ select FSL_ESDHC_IMX
+ help
+ This enables the Ultra Secured Digital Host Controller enhancements
+
endmenu
config SYS_FSL_ERRATUM_ESDHC111