Merge tag 'fixes-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot...

[platform/kernel/u-boot.git] / drivers / misc / Kconfig

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index cb8b5c0..f18aa8f 100644 (file)
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -59,6 +59,15 @@ config ROCKCHIP_EFUSE
          extended (by porting the read function from the Linux kernel sources)
          to support other recent Rockchip devices.
 
+config ROCKCHIP_OTP
+       bool "Rockchip OTP Support"
+       depends on MISC
+       help
+         Enable (read-only) access for the one-time-programmable memory block
+         found in Rockchip SoCs: accesses can either be made using byte
+         addressing and a length or through child-nodes that are generated
+         based on the e-fuse map retrieved from the DTS.
+
 config VEXPRESS_CONFIG
        bool "Enable support for Arm Versatile Express config bus"
        depends on MISC
@@ -88,6 +97,7 @@ config CROS_EC
 
 config SPL_CROS_EC
        bool "Enable Chrome OS EC in SPL"
+       depends on SPL
        help
          Enable access to the Chrome OS EC in SPL. This is a separate
          microcontroller typically available on a SPI bus on Chromebooks. It
@@ -97,6 +107,7 @@ config SPL_CROS_EC
 
 config TPL_CROS_EC
        bool "Enable Chrome OS EC in TPL"
+       depends on TPL
        help
          Enable access to the Chrome OS EC in TPL. This is a separate
          microcontroller typically available on a SPI bus on Chromebooks. It
@@ -192,6 +203,15 @@ config FSL_SEC_MON
          Security Monitor can be transitioned on any security failures,
          like software violations or hardware security violations.
 
+config IRQ
+       bool "Intel Interrupt controller"
+       depends on X86 || SANDBOX
+       help
+         This enables support for Intel interrupt controllers, including ITSS.
+         Some devices have extra features, such as Apollo Lake. The
+         device has its own uclass since there are several operations
+         involved.
+
 config JZ4780_EFUSE
        bool "Ingenic JZ4780 eFUSE support"
        depends on ARCH_JZ47XX
@@ -200,7 +220,7 @@ config JZ4780_EFUSE
 
 config MXC_OCOTP
        bool "Enable MXC OCOTP Driver"
-       depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610
+       depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
        default y
        help
          If you say Y here, you will get support for the One Time
@@ -215,6 +235,39 @@ config NUVOTON_NCT6102D
          disable the legacy UART, the watchdog or other devices
          in the Nuvoton Super IO chips on X86 platforms.
 
+config P2SB
+       bool "Intel Primary-to-Sideband Bus"
+       depends on X86 || SANDBOX
+       help
+         This enables support for the Intel Primary-to-Sideband bus,
+         abbreviated to P2SB. The P2SB is used to access various peripherals
+         such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
+         space. The space is segmented into different channels and peripherals
+         are accessed by device-specific means within those channels. Devices
+         should be added in the device tree as subnodes of the P2SB. A
+         Peripheral Channel Register? (PCR) API is provided to access those
+         devices - see pcr_readl(), etc.
+
+config SPL_P2SB
+       bool "Intel Primary-to-Sideband Bus in SPL"
+       depends on SPL && (X86 || SANDBOX)
+       help
+         The Primary-to-Sideband bus is used to access various peripherals
+         through memory-mapped I/O in a large chunk of PCI space. The space is
+         segmented into different channels and peripherals are accessed by
+         device-specific means within those channels. Devices should be added
+         in the device tree as subnodes of the p2sb.
+
+config TPL_P2SB
+       bool "Intel Primary-to-Sideband Bus in TPL"
+       depends on TPL && (X86 || SANDBOX)
+       help
+         The Primary-to-Sideband bus is used to access various peripherals
+         through memory-mapped I/O in a large chunk of PCI space. The space is
+         segmented into different channels and peripherals are accessed by
+         device-specific means within those channels. Devices should be added
+         in the device tree as subnodes of the p2sb.
+
 config PWRSEQ
        bool "Enable power-sequencing drivers"
        depends on DM
@@ -410,4 +463,22 @@ config IHS_FPGA
          by the devices. This driver supports both CON and CPU variants of the
          devices, depending on the device tree entry.
 
+config MICROCHIP_FLEXCOM
+       bool "Enable Microchip Flexcom driver"
+       depends on MISC
+       help
+         The Atmel Flexcom is just a wrapper which embeds a SPI controller,
+         an I2C controller and an USART.
+         Only one function can be used at a time and is chosen at boot time
+         according to the device tree.
+
+config K3_AVS0
+       depends on ARCH_K3 && SPL_DM_REGULATOR
+       bool "AVS class 0 support for K3 devices"
+       help
+         K3 devices have the optimized voltage values for the main voltage
+         domains stored in efuse within the VTM IP. This driver reads the
+         optimized voltage from the efuse, so that it can be programmed
+         to the PMIC on board.
+
 endmenu