config SPL_MISC
bool "Enable Driver Model for Misc drivers in SPL"
depends on SPL_DM
+ default MISC
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
config TPL_MISC
bool "Enable Driver Model for Misc drivers in TPL"
depends on TPL_DM
+ default MISC
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
+config VPL_MISC
+ bool "Enable Driver Model for Misc drivers in VPL"
+ depends on VPL_DM
+ default MISC
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
config ATSHA204A
bool "Support for Atmel ATSHA204A module"
+ select BITREVERSE
depends on MISC
help
Enable support for I2C connected Atmel's ATSHA204A
CryptoAuthentication module found for example on the Turris Omnia
board.
+config GATEWORKS_SC
+ bool "Gateworks System Controller Support"
+ depends on MISC
+ help
+ Enable access for the Gateworks System Controller used on Gateworks
+ boards to provide a boot watchdog, power control, temperature monitor,
+ voltage ADCs, and EEPROM.
+
config ROCKCHIP_EFUSE
bool "Rockchip e-fuse support"
depends on MISC
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config SIFIVE_OTP
+ bool "SiFive eMemory OTP driver"
+ depends on MISC
+ help
+ Enable support for reading and writing the eMemory OTP on the
+ SiFive SoCs.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
+config VPL_CROS_EC
+ bool "Enable Chrome OS EC in VPL"
+ depends on VPL
+ help
+ Enable access to the Chrome OS EC in VPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
+config VPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in VPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
+config VPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in VPL"
+ depends on VPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
+config IRQ
+ bool "Interrupt controller"
+ help
+ This enables support for interrupt controllers, including ITSS.
+ Some devices have extra features, such as Apollo Lake. The
+ device has its own uclass since there are several operations
+ involved.
+
config JZ4780_EFUSE
bool "Ingenic JZ4780 eFUSE support"
depends on ARCH_JZ47XX
Programmable memory pages that are stored on the some
Freescale i.MX processors.
+config SPL_MXC_OCOTP
+ bool "Enable MXC OCOTP driver in SPL"
+ depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+ default y
+ help
+ If you say Y here, you will get support for the One Time
+ Programmable memory pages, that are stored on some
+ Freescale i.MX processors, in SPL.
+
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
disable the legacy UART, the watchdog or other devices
in the Nuvoton Super IO chips on X86 platforms.
+config P2SB
+ bool "Intel Primary to Sideband Bridge"
+ depends on X86 || SANDBOX
+ help
+ This enables support for the Intel Primary to Sideband Bridge,
+ abbreviated to P2SB. The P2SB is used to access various peripherals
+ such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
+ space. The space is segmented into different channels and peripherals
+ are accessed by device-specific means within those channels. Devices
+ should be added in the device tree as subnodes of the P2SB. A
+ Peripheral Channel Register? (PCR) API is provided to access those
+ devices - see pcr_readl(), etc.
+
+config SPL_P2SB
+ bool "Intel Primary to Sideband Bridge in SPL"
+ depends on SPL && (X86 || SANDBOX)
+ help
+ The Primary to Sideband Bridge is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
+config TPL_P2SB
+ bool "Intel Primary to Sideband Bridge in TPL"
+ depends on TPL && (X86 || SANDBOX)
+ help
+ The Primary to Sideband Bridge is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
config STM32_RCC
bool "Enable RCC driver for the STM32 SoC's family"
- depends on (STM32 || ARCH_STM32MP) && MISC
+ depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
help
Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
block) is responsible of the management of the clock and reset
can make requests to the BPMP. This driver is similar to an MFD
driver in the Linux kernel.
+config TEST_DRV
+ bool "Enable support for test drivers"
+ default y if SANDBOX
+ help
+ This enables drivers and uclasses that provides a way of testing the
+ operations of memory allocation and driver/uclass methods in driver
+ model. This should only be enabled for testing as it is not useful for
+ anything else.
+
config TWL4030_LED
bool "Enable TWL4030 LED controller"
help
config QFW
bool
help
- Hidden option to enable QEMU fw_cfg interface. This will be selected by
- either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+ Hidden option to enable QEMU fw_cfg interface and uclass. This will
+ be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
+config QFW_PIO
+ bool
+ depends on QFW
+ help
+ Hidden option to enable PIO QEMU fw_cfg interface. This will be
+ selected by the appropriate QEMU board.
+
+config QFW_MMIO
+ bool
+ depends on QFW
+ help
+ Hidden option to enable MMIO QEMU fw_cfg interface. This will be
+ selected by the appropriate QEMU board.
config I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs"
This option is an SPL-variant of the I2C_EEPROM option.
See the help of I2C_EEPROM for details.
-config ZYNQ_GEM_I2C_MAC_OFFSET
- hex "Set the I2C MAC offset"
- default 0x0
- depends on DM_I2C
- help
- Set the MAC offset for i2C.
-
-if I2C_EEPROM
-
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
+ depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
default 0
-config SYS_I2C_EEPROM_BUS
- int "I2C bus of the EEPROM device."
- default 0
-
-config SYS_EEPROM_SIZE
- int "Size in bytes of the EEPROM device"
- default 256
-
-config SYS_EEPROM_PAGE_WRITE_BITS
- int "Number of bits used to address bytes in a single page"
- default 0
- help
- The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
- A 64 byte page, for example would require six bits.
-
-config SYS_EEPROM_PAGE_WRITE_DELAY_MS
- int "Number of milliseconds to delay between page writes"
- default 0
-
-config SYS_I2C_EEPROM_ADDR_LEN
- int "Length in bytes of the EEPROM memory array address"
- default 1
- help
- Note: This is NOT the chip address length!
+if I2C_EEPROM
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
- default 0
+ default 0x0
help
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
+config SPL_FS_LOADER
+ bool "Enable loader driver for file system"
+ help
+ This is file system generic loader which can be used to load
+ the file image from the storage into target such as memory.
+
+ The consumer driver would then use this loader to program whatever,
+ ie. the FPGA device.
+
config GDSYS_SOC
bool "Enable gdsys SOC driver"
depends on MISC
gdsys devices, which supply the majority of the functionality offered
by the devices. This driver supports both CON and CPU variants of the
devices, depending on the device tree entry.
+config ESM_K3
+ bool "Enable K3 ESM driver"
+ depends on ARCH_K3
+ help
+ Support ESM (Error Signaling Module) on TI K3 SoCs.
config MICROCHIP_FLEXCOM
bool "Enable Microchip Flexcom driver"
optimized voltage from the efuse, so that it can be programmed
to the PMIC on board.
+config ESM_PMIC
+ bool "Enable PMIC ESM driver"
+ depends on DM_PMIC
+ help
+ Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
+ typically to reboot the board in error condition.
+
+config FSL_IFC
+ bool
+
+config SL28CPLD
+ bool "Enable Kontron sl28cpld multi-function driver"
+ depends on DM_I2C
+ help
+ Support for the Kontron sl28cpld management controller. This is
+ the base driver which provides common access methods for the
+ sub-drivers.
+
endmenu
projects / platform / kernel / u-boot.git / blobdiff