#define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n))
#define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n))
+#define CAMSS_CSI_PHY_LN_CLK 1
#define CAMSS_CSI_PHY_GLBL_RESET 0x140
#define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x144
#define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x164
#define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec
#define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f4
+static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
+{
+ u8 lane_mask;
+ int i;
+
+ lane_mask = 1 << CAMSS_CSI_PHY_LN_CLK;
+
+ for (i = 0; i < lane_cfg->num_data; i++)
+ lane_mask |= 1 << lane_cfg->data[i].pos;
+
+ return lane_mask;
+}
+
static void csiphy_hw_version_read(struct csiphy_device *csiphy,
struct device *dev)
{
for (i = 0; i <= c->num_data; i++) {
if (i == c->num_data)
- l = c->clk.pos;
+ l = CAMSS_CSI_PHY_LN_CLK;
else
l = c->data[i].pos;
for (i = 0; i <= c->num_data; i++) {
if (i == c->num_data)
- l = c->clk.pos;
+ l = CAMSS_CSI_PHY_LN_CLK;
else
l = c->data[i].pos;
}
const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = {
+ .get_lane_mask = csiphy_get_lane_mask,
.hw_version_read = csiphy_hw_version_read,
.reset = csiphy_reset,
.lanes_enable = csiphy_lanes_enable,