usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver

[platform/kernel/u-boot.git] / drivers / i2c / designware_i2c.h

diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 270c29c..049976e 100644 (file)
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -1,13 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 #ifndef __DW_I2C_H_
 #define __DW_I2C_H_
 
+#include <clk.h>
+#include <i2c.h>
+#include <reset.h>
+#include <linux/bitops.h>
+
 struct i2c_regs {
        u32 ic_con;             /* 0x00 */
        u32 ic_tar;             /* 0x04 */
@@ -42,20 +46,32 @@ struct i2c_regs {
        u32 ic_rxflr;           /* 0x78 */
        u32 ic_sda_hold;        /* 0x7c */
        u32 ic_tx_abrt_source;  /* 0x80 */
-       u8 res1[0x18];          /* 0x84 */
+       u32 slv_data_nak_only;
+       u32 dma_cr;
+       u32 dma_tdlr;
+       u32 dma_rdlr;
+       u32 sda_setup;
+       u32 ack_general_call;
        u32 ic_enable_status;   /* 0x9c */
+       u32 fs_spklen;
+       u32 hs_spklen;
+       u32 clr_restart_det;
+       u8 reserved[0xf4 - 0xac];
+       u32 comp_param1;        /* 0xf4 */
+       u32 comp_version;
+       u32 comp_type;
 };
 
-#if !defined(IC_CLK)
-#define IC_CLK                 166
-#endif
-#define NANO_TO_MICRO          1000
+#define IC_CLK                 166666666
+#define NANO_TO_KILO           1000000
 
 /* High and low times in different speed modes (in ns) */
 #define MIN_SS_SCL_HIGHTIME    4000
 #define MIN_SS_SCL_LOWTIME     4700
 #define MIN_FS_SCL_HIGHTIME    600
 #define MIN_FS_SCL_LOWTIME     1300
+#define MIN_FP_SCL_HIGHTIME    260
+#define MIN_FP_SCL_LOWTIME     500
 #define MIN_HS_SCL_HIGHTIME    60
 #define MIN_HS_SCL_LOWTIME     160
 
@@ -96,7 +112,7 @@ struct i2c_regs {
 #define IC_TX_EMPTY            0x0010
 #define IC_TX_OVER             0x0008
 #define IC_RX_FULL             0x0004
-#define IC_RX_OVER             0x0002
+#define IC_RX_OVER             0x0002
 #define IC_RX_UNDER            0x0001
 
 /* fifo threshold register definitions */
@@ -123,13 +139,93 @@ struct i2c_regs {
 #define IC_STATUS_TFNF         0x0002
 #define IC_STATUS_ACT          0x0001
 
-/* Speed Selection */
-#define IC_SPEED_MODE_STANDARD 1
-#define IC_SPEED_MODE_FAST     2
-#define IC_SPEED_MODE_MAX      3
+#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
+#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      (BIT(2) | BIT(3))
+
+/**
+ * struct dw_scl_sda_cfg - I2C timing configuration
+ *
+ * @ss_hcnt: Standard speed high time in ns
+ * @fs_hcnt: Fast speed high time in ns
+ * @hs_hcnt: High speed high time in ns
+ * @ss_lcnt: Standard speed low time in ns
+ * @fs_lcnt: Fast speed low time in ns
+ * @hs_lcnt: High speed low time in ns
+ * @sda_hold: SDA hold time
+ */
+struct dw_scl_sda_cfg {
+       u32 ss_hcnt;
+       u32 fs_hcnt;
+       u32 hs_hcnt;
+       u32 ss_lcnt;
+       u32 fs_lcnt;
+       u32 hs_lcnt;
+       u32 sda_hold;
+};
+
+/**
+ * struct dw_i2c_speed_config - timings to use for a particular speed
+ *
+ * This holds calculated values to be written to the I2C controller. Each value
+ * is represented as a number of IC clock cycles.
+ *
+ * @scl_lcnt: Low count value for SCL
+ * @scl_hcnt: High count value for SCL
+ * @sda_hold: Data hold count
+ * @speed_mode: Speed mode being used
+ */
+struct dw_i2c_speed_config {
+       /* SCL high and low period count */
+       u16 scl_lcnt;
+       u16 scl_hcnt;
+       u32 sda_hold;
+       enum i2c_speed_mode speed_mode;
+};
+
+/**
+ * struct dw_i2c - private information for the bus
+ *
+ * @regs: Registers pointer
+ * @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
+ * @resets: Resets for the I2C controller
+ * @scl_rise_time_ns: Configured SCL rise time in nanoseconds
+ * @scl_fall_time_ns: Configured SCL fall time in nanoseconds
+ * @sda_hold_time_ns: Configured SDA hold time in nanoseconds
+ * @has_spk_cnt: true if the spike-count register is present
+ * @clk: Clock input to the I2C controller
+ */
+struct dw_i2c {
+       struct i2c_regs *regs;
+       struct dw_scl_sda_cfg *scl_sda_cfg;
+       struct reset_ctl_bulk resets;
+       u32 scl_rise_time_ns;
+       u32 scl_fall_time_ns;
+       u32 sda_hold_time_ns;
+       bool has_spk_cnt;
+#if CONFIG_IS_ENABLED(CLK)
+       struct clk clk;
+#endif
+       struct dw_i2c_speed_config config;
+};
 
-#define I2C_MAX_SPEED          3400000
-#define I2C_FAST_SPEED         400000
-#define I2C_STANDARD_SPEED     100000
+extern const struct dm_i2c_ops designware_i2c_ops;
+
+int designware_i2c_probe(struct udevice *bus);
+int designware_i2c_remove(struct udevice *dev);
+int designware_i2c_of_to_plat(struct udevice *bus);
+
+/**
+ * dw_i2c_gen_speed_config() - Calculate config info from requested speed
+ *
+ * Calculate the speed config from the given @speed_hz and return it so that
+ * it can be incorporated in ACPI tables
+ *
+ * @dev: I2C bus to check
+ * @speed_hz: Requested speed in Hz
+ * @config: Returns config to use for that speed
+ * Return: 0 if OK, -ve on error
+ */
+int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
+                           struct dw_i2c_speed_config *config);
 
 #endif /* __DW_I2C_H_ */