Merge remote-tracking branch 'stable/linux-5.15.y' into rpi-5.15.y

[platform/kernel/linux-rpi.git] / drivers / gpu / drm / vc4 / vc4_regs.h

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 8ac2f08..82b0fda 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -499,6 +499,28 @@
 #define SCALER_DLIST_START                      0x00002000
 #define SCALER_DLIST_SIZE                       0x00004000
 
+/* Gamma PWL for each channel. 16 points for each of 4 colour channels (alpha
+ * only on channel 2). 8 bytes per entry, offsets first, then gradient:
+ *   Y = GRAD * X + C
+ *
+ * Values for X and C are left justified, and vary depending on the width of
+ * the HVS channel:
+ *    8-bit pipeline: X uses [31:24], C is U8.8 format, and GRAD is U4.8.
+ *   12-bit pipeline: X uses [31:20], C is U12.4 format, and GRAD is U4.8.
+ *
+ * The 3 HVS channels start at 0x400 offsets (ie chan 1 starts at 0x2400, and
+ * chan 2 at 0x2800).
+ */
+#define SCALER5_DSPGAMMA_NUM_POINTS            16
+#define SCALER5_DSPGAMMA_START                 0x00002000
+#define SCALER5_DSPGAMMA_CHAN_OFFSET           0x400
+# define SCALER5_DSPGAMMA_OFF_X_MASK           VC4_MASK(31, 20)
+# define SCALER5_DSPGAMMA_OFF_X_SHIFT          20
+# define SCALER5_DSPGAMMA_OFF_C_MASK           VC4_MASK(15, 0)
+# define SCALER5_DSPGAMMA_OFF_C_SHIFT          0
+# define SCALER5_DSPGAMMA_GRAD_MASK            VC4_MASK(11, 0)
+# define SCALER5_DSPGAMMA_GRAD_SHIFT           0
+
 #define SCALER5_DLIST_START                    0x00004000
 
 # define VC4_HDMI_SW_RESET_FORMAT_DETECT       BIT(1)
@@ -782,8 +804,27 @@ enum {
 # define VC4_HD_CSC_CTL_RGB2YCC                        BIT(1)
 # define VC4_HD_CSC_CTL_ENABLE                 BIT(0)
 
+# define VC5_MT_CP_CSC_CTL_USE_444_TO_422      BIT(6)
+# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \
+                                               VC4_MASK(5, 4)
+# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \
+                                               3
+# define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
+# define VC5_MT_CP_CSC_CTL_ENABLE              BIT(2)
+# define VC5_MT_CP_CSC_CTL_MODE_MASK           VC4_MASK(1, 0)
+
+# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \
+                                               VC4_MASK(7, 6)
+# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \
+                                               2
+
 # define VC4_DVP_HT_CLOCK_STOP_PIXEL           BIT(1)
 
+# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \
+                                               VC4_MASK(3, 2)
+# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \
+                                               2
+
 /* HVS display list information. */
 #define HVS_BOOTLOADER_DLIST_END                32
 
@@ -816,16 +857,19 @@ enum hvs_pixel_format {
 /* Note: the LSB is the rightmost character shown.  Only valid for
  * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
  */
+/* For modes 332, 4444, 555, 5551, 6666, 8888, 10:10:10:2 */
 #define HVS_PIXEL_ORDER_RGBA                   0
 #define HVS_PIXEL_ORDER_BGRA                   1
 #define HVS_PIXEL_ORDER_ARGB                   2
 #define HVS_PIXEL_ORDER_ABGR                   3
 
+/* For modes 666 and 888 (4 & 5) */
 #define HVS_PIXEL_ORDER_XBRG                   0
 #define HVS_PIXEL_ORDER_XRBG                   1
 #define HVS_PIXEL_ORDER_XRGB                   2
 #define HVS_PIXEL_ORDER_XBGR                   3
 
+/* For YCbCr modes (8-12, and 17) */
 #define HVS_PIXEL_ORDER_XYCBCR                 0
 #define HVS_PIXEL_ORDER_XYCRCB                 1
 #define HVS_PIXEL_ORDER_YXCBCR                 2
@@ -983,7 +1027,10 @@ enum hvs_pixel_format {
 #define SCALER_CSC0_COEF_CR_OFS_SHIFT          0
 #define SCALER_CSC0_ITR_R_601_5                        0x00f00000
 #define SCALER_CSC0_ITR_R_709_3                        0x00f00000
+#define SCALER_CSC0_ITR_R_2020                 0x00f00000
 #define SCALER_CSC0_JPEG_JFIF                  0x00000000
+#define SCALER_CSC0_ITR_R_709_3_FR             0x00000000
+#define SCALER_CSC0_ITR_R_2020_FR              0x00000000
 
 /* S2.8 contribution of Cb to Green */
 #define SCALER_CSC1_COEF_CB_GRN_MASK           VC4_MASK(31, 22)
@@ -998,8 +1045,11 @@ enum hvs_pixel_format {
 #define SCALER_CSC1_COEF_CR_BLU_MASK           VC4_MASK(1, 0)
 #define SCALER_CSC1_COEF_CR_BLU_SHIFT          0
 #define SCALER_CSC1_ITR_R_601_5                        0xe73304a8
-#define SCALER_CSC1_ITR_R_709_3                        0xf2b784a8
-#define SCALER_CSC1_JPEG_JFIF                  0xea34a400
+#define SCALER_CSC1_ITR_R_709_3                        0xf27784a8
+#define SCALER_CSC1_ITR_R_2020                 0xf43594a8
+#define SCALER_CSC1_JPEG_JFIF                  0xea349400
+#define SCALER_CSC1_ITR_R_709_3_FR             0xf4388400
+#define SCALER_CSC1_ITR_R_2020_FR              0xf5b6d400
 
 /* S2.8 contribution of Cb to Red */
 #define SCALER_CSC2_COEF_CB_RED_MASK           VC4_MASK(29, 20)
@@ -1010,9 +1060,12 @@ enum hvs_pixel_format {
 /* S2.8 contribution of Cb to Blue */
 #define SCALER_CSC2_COEF_CB_BLU_MASK           VC4_MASK(19, 10)
 #define SCALER_CSC2_COEF_CB_BLU_SHIFT          10
-#define SCALER_CSC2_ITR_R_601_5                        0x00066204
-#define SCALER_CSC2_ITR_R_709_3                        0x00072a1c
-#define SCALER_CSC2_JPEG_JFIF                  0x000599c5
+#define SCALER_CSC2_ITR_R_601_5                        0x00066604
+#define SCALER_CSC2_ITR_R_709_3                        0x00072e1d
+#define SCALER_CSC2_ITR_R_2020                 0x0006b624
+#define SCALER_CSC2_JPEG_JFIF                  0x00059dc6
+#define SCALER_CSC2_ITR_R_709_3_FR             0x00064ddb
+#define SCALER_CSC2_ITR_R_2020_FR              0x0005e5e2
 
 #define SCALER_TPZ0_VERT_RECALC                        BIT(31)
 #define SCALER_TPZ0_SCALE_MASK                 VC4_MASK(28, 8)