drm/nouveau: replace nv04_graph_fifo_access() use with direct reg bashing

[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / gpu / drm / nouveau / nv10_graph.c

diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 0930c6c..2567522 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -708,8 +708,8 @@ static void nv10_graph_load_dma_vtxbuf(struct nouveau_channel *chan,
                0x2c000000 | chan->id << 20 | subchan << 16 | 0x18c);
        nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
        nv_mask(dev, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
-       nv04_graph_fifo_access(dev, true);
-       nv04_graph_fifo_access(dev, false);
+       nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
+       nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
 
        /* Restore the FIFO state */
        for (i = 0; i < ARRAY_SIZE(fifo); i++)
@@ -879,13 +879,13 @@ nv10_graph_context_del(struct nouveau_channel *chan, int engine)
        unsigned long flags;
 
        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
-       nv04_graph_fifo_access(dev, false);
+       nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
 
        /* Unload the context if it's the currently active one */
        if (nv10_graph_channel(dev) == chan)
                nv10_graph_unload_context(dev);
 
-       nv04_graph_fifo_access(dev, true);
+       nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
        /* Free the context resources */