drm/msms/dp: fixed link clock divider bits be over written in BPC unknown case

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / msm / dp / dp_ctrl.c

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index a7a5c7e..fb588fd 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -135,11 +135,6 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
        tbd = dp_link_get_test_bits_depth(ctrl->link,
                        ctrl->panel->dp_mode.bpp);
 
-       if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
-               pr_debug("BIT_DEPTH not set. Configure default\n");
-               tbd = DP_TEST_BIT_DEPTH_8;
-       }
-
        config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
 
        /* Num of Lanes */
@@ -1774,13 +1769,6 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
                return rc;
 
        while (--link_train_max_retries) {
-               rc = dp_ctrl_reinitialize_mainlink(ctrl);
-               if (rc) {
-                       DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
-                                       rc);
-                       break;
-               }
-
                training_step = DP_TRAINING_NONE;
                rc = dp_ctrl_setup_main_link(ctrl, &training_step);
                if (rc == 0) {
@@ -1832,6 +1820,12 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
                        /* stop link training before start re training  */
                        dp_ctrl_clear_training_pattern(ctrl);
                }
+
+               rc = dp_ctrl_reinitialize_mainlink(ctrl);
+               if (rc) {
+                       DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc);
+                       break;
+               }
        }
 
        if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)