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drm/msm/dpu: correct indentation for CTL definitions
[platform/kernel/linux-rpi.git] / drivers / gpu / drm / msm / disp / dpu1 / catalog / dpu_4_0_sdm845.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index ceca741..7da35be 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -26,52 +26,45 @@ static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
        .highest_bank_bit = 0x2,
 };
 
-static const struct dpu_mdp_cfg sdm845_mdp[] = {
-       {
-       .name = "top_0", .id = MDP_TOP,
+static const struct dpu_mdp_cfg sdm845_mdp = {
+       .name = "top_0",
        .base = 0x0, .len = 0x45c,
-       .features = BIT(DPU_MDP_AUDIO_SELECT),
-       .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
-       .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
-       .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
-       .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
-       .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
-       .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
-       .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
-       .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+       .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
+       .clk_ctrls = {
+               [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+               [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+               [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+               [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+               [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+               [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+               [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+               [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
        },
 };
 
 static const struct dpu_ctl_cfg sdm845_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0xe4,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0xe4,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0xe4,
-       .features = 0,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0xe4,
-       .features = 0,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x1800, .len = 0xe4,
-       .features = 0,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0xe4,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0xe4,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0xe4,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0xe4,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x1800, .len = 0xe4,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
        },
 };
 
@@ -96,30 +89,41 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
 
 static const struct dpu_lm_cfg sdm845_lm[] = {
        LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
-               &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
+               &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
        LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
-               &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
+               &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
        LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
-               &sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
+               &sdm845_lm_sblk, PINGPONG_2, LM_5, DSPP_2),
        LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
-               &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
+               &sdm845_lm_sblk, PINGPONG_NONE, 0, DSPP_3),
        LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
-               &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
+               &sdm845_lm_sblk, PINGPONG_NONE, 0, 0),
        LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
                &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
 };
 
+static const struct dpu_dspp_cfg sdm845_dspp[] = {
+       DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+                &sdm845_dspp_sblk),
+       DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
+                &sdm845_dspp_sblk),
+       DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
+                &sdm845_dspp_sblk),
+       DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
+                &sdm845_dspp_sblk),
+};
+
 static const struct dpu_pingpong_cfg sdm845_pp[] = {
-       PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
+       PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
-       PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
+       PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
-       PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
+       PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
-       PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
+       PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 };
@@ -132,10 +136,18 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sdm845_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
-       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
-       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
+       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
 };
 
 static const struct dpu_perf_cfg sdm845_perf_data = {
@@ -177,14 +189,15 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
 const struct dpu_mdss_cfg dpu_sdm845_cfg = {
        .caps = &sdm845_dpu_caps,
        .ubwc = &sdm845_ubwc_cfg,
-       .mdp_count = ARRAY_SIZE(sdm845_mdp),
-       .mdp = sdm845_mdp,
+       .mdp = &sdm845_mdp,
        .ctl_count = ARRAY_SIZE(sdm845_ctl),
        .ctl = sdm845_ctl,
        .sspp_count = ARRAY_SIZE(sdm845_sspp),
        .sspp = sdm845_sspp,
        .mixer_count = ARRAY_SIZE(sdm845_lm),
        .mixer = sdm845_lm,
+       .dspp_count = ARRAY_SIZE(sdm845_dspp),
+       .dspp = sdm845_dspp,
        .pingpong_count = ARRAY_SIZE(sdm845_pp),
        .pingpong = sdm845_pp,
        .dsc_count = ARRAY_SIZE(sdm845_dsc),
@@ -193,8 +206,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
        .intf = sdm845_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sdm845_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
Domain: System / Kernel;