drm/i915: use hsw rps tuning values everywhere on gen6+

[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / gpu / drm / i915 / intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58c07cd..1881c8c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2441,17 +2441,10 @@ static void gen6_enable_rps(struct drm_device *dev)
                   dev_priv->max_delay << 24 |
                   dev_priv->min_delay << 16);
 
-       if (IS_HASWELL(dev)) {
-               I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-               I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
-               I915_WRITE(GEN6_RP_UP_EI, 66000);
-               I915_WRITE(GEN6_RP_DOWN_EI, 350000);
-       } else {
-               I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
-               I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
-               I915_WRITE(GEN6_RP_UP_EI, 100000);
-               I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
-       }
+       I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+       I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+       I915_WRITE(GEN6_RP_UP_EI, 66000);
+       I915_WRITE(GEN6_RP_DOWN_EI, 350000);
 
        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
        I915_WRITE(GEN6_RP_CONTROL,