Merge drm/drm-next into drm-intel-next

[platform/kernel/linux-rpi.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93f3b7e..f9d2f84 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1728,16 +1728,27 @@
 #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
 #define PVC_RP_STATE_CAP       _MMIO(0x281014)
 
+#define MTL_RP_STATE_CAP       _MMIO(0x138000)
+#define MTL_MEDIAP_STATE_CAP   _MMIO(0x138020)
+#define   MTL_RP0_CAP_MASK     REG_GENMASK(8, 0)
+#define   MTL_RPN_CAP_MASK     REG_GENMASK(24, 16)
+
+#define MTL_GT_RPE_FREQUENCY   _MMIO(0x13800c)
+#define MTL_MPE_FREQUENCY      _MMIO(0x13802c)
+#define   MTL_RPE_MASK         REG_GENMASK(8, 0)
+
 #define GT0_PERF_LIMIT_REASONS         _MMIO(0x1381a8)
 #define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
-#define   PROCHOT_MASK                 REG_BIT(1)
-#define   THERMAL_LIMIT_MASK           REG_BIT(2)
-#define   RATL_MASK                    REG_BIT(6)
-#define   VR_THERMALERT_MASK           REG_BIT(7)
-#define   VR_TDC_MASK                  REG_BIT(8)
-#define   POWER_LIMIT_4_MASK           REG_BIT(9)
-#define   POWER_LIMIT_1_MASK           REG_BIT(11)
-#define   POWER_LIMIT_2_MASK           REG_BIT(12)
+#define   PROCHOT_MASK                 REG_BIT(0)
+#define   THERMAL_LIMIT_MASK           REG_BIT(1)
+#define   RATL_MASK                    REG_BIT(5)
+#define   VR_THERMALERT_MASK           REG_BIT(6)
+#define   VR_TDC_MASK                  REG_BIT(7)
+#define   POWER_LIMIT_4_MASK           REG_BIT(8)
+#define   POWER_LIMIT_1_MASK           REG_BIT(10)
+#define   POWER_LIMIT_2_MASK           REG_BIT(11)
+#define   GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
+#define MTL_MEDIA_PERF_LIMIT_REASONS   _MMIO(0x138030)
 
 #define CHV_CLK_CTL1                   _MMIO(0x101100)
 #define VLV_CLK_CTL2                   _MMIO(0x101104)
@@ -6585,6 +6596,12 @@
 #define   DG1_PCODE_STATUS                     0x7E
 #define     DG1_UNCORE_GET_INIT_STATUS         0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE    0x1
+#define   PCODE_POWER_SETUP                    0x7C
+#define     POWER_SETUP_SUBCOMMAND_READ_I1     0x4
+#define     POWER_SETUP_SUBCOMMAND_WRITE_I1    0x5
+#define            POWER_SETUP_I1_WATTS                REG_BIT(31)
+#define            POWER_SETUP_I1_SHIFT                6       /* 10.6 fixed point format */
+#define            POWER_SETUP_I1_DATA_MASK            REG_GENMASK(15, 0)
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US    0x23
 #define   XEHP_PCODE_FREQUENCY_CONFIG          0x6e    /* xehpsdv, pvc */
 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
@@ -7721,8 +7738,13 @@ enum skl_power_gate {
                                                           _ICL_PIPE_DSS_CTL2_PB, \
                                                           _ICL_PIPE_DSS_CTL2_PC)
 
+#define GGC                            _MMIO(0x108040)
+#define   GMS_MASK                     REG_GENMASK(15, 8)
+#define   GGMS_MASK                    REG_GENMASK(7, 6)
+
 #define GEN12_GSMBASE                  _MMIO(0x108100)
 #define GEN12_DSMBASE                  _MMIO(0x1080C0)
+#define   GEN12_BDSM_MASK              REG_GENMASK64(63, 20)
 
 #define XEHP_CLOCK_GATE_DIS            _MMIO(0x101014)
 #define   SGSI_SIDECLK_DIS             REG_BIT(17)