Merge drm/drm-next into drm-intel-gt-next

[platform/kernel/linux-rpi.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c87d77..6104f7a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1837,6 +1837,17 @@
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
 #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
 
+#define GT0_PERF_LIMIT_REASONS         _MMIO(0x1381a8)
+#define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
+#define   PROCHOT_MASK                 REG_BIT(1)
+#define   THERMAL_LIMIT_MASK           REG_BIT(2)
+#define   RATL_MASK                    REG_BIT(6)
+#define   VR_THERMALERT_MASK           REG_BIT(7)
+#define   VR_TDC_MASK                  REG_BIT(8)
+#define   POWER_LIMIT_4_MASK           REG_BIT(9)
+#define   POWER_LIMIT_1_MASK           REG_BIT(11)
+#define   POWER_LIMIT_2_MASK           REG_BIT(12)
+
 #define CHV_CLK_CTL1                   _MMIO(0x101100)
 #define VLV_CLK_CTL2                   _MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT  28
@@ -8465,6 +8476,9 @@ enum skl_power_gate {
 #define   SGGI_DIS                     REG_BIT(15)
 #define   SGR_DIS                      REG_BIT(13)
 
+#define XEHPSDV_TILE0_ADDR_RANGE       _MMIO(0x4900)
+#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT  8
+
 #define XEHPSDV_FLAT_CCS_BASE_ADDR     _MMIO(0x4910)
 #define   XEHPSDV_CCS_BASE_SHIFT       8