Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/drm-intel...

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5375b21..0023c02 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4352,6 +4352,7 @@ enum {
 #define   VRR_CTL_IGN_MAX_SHIFT                REG_BIT(30)
 #define   VRR_CTL_FLIP_LINE_EN         REG_BIT(29)
 #define   VRR_CTL_LINE_COUNT_MASK      REG_GENMASK(10, 3)
+#define   VRR_CTL_LINE_COUNT(x)                REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
 #define   VRR_CTL_SW_FULLLINE_COUNT    REG_BIT(0)
 
 #define _TRANS_VRR_VMAX_A              0x60424
@@ -10851,8 +10852,10 @@ enum skl_power_gate {
 #define  CNL_DRAM_RANK_3                       (0x2 << 9)
 #define  CNL_DRAM_RANK_4                       (0x3 << 9)
 
-/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
- * since on HSW we can't write to it using I915_WRITE. */
+/*
+ * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
+ * since on HSW we can't write to it using intel_uncore_write.
+ */
 #define D_COMP_HSW                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
 #define D_COMP_BDW                     _MMIO(0x138144)
 #define  D_COMP_RCOMP_IN_PROGRESS      (1 << 9)