Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/drm-intel...

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / i915 / gvt / handlers.c

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 91245d2..3a4f559 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1489,7 +1489,8 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
        const struct intel_engine_cs *engine =
                intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
 
-       if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
+       if (value != 0 &&
+           !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
                gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
                              offset, value);
                return -EINVAL;
@@ -1650,6 +1651,34 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
        return 0;
 }
 
+/**
+ * FixMe:
+ * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
+ * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
+ * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
+ * these MI_BATCH_BUFFER.
+ * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
+ * PML4 PTE: PAT(0) PCD(1) PWT(1).
+ * The performance is still expected to be low, will need further improvement.
+ */
+static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
+                             void *p_data, unsigned int bytes)
+{
+       u64 pat =
+               GEN8_PPAT(0, CHV_PPAT_SNOOP) |
+               GEN8_PPAT(1, 0) |
+               GEN8_PPAT(2, 0) |
+               GEN8_PPAT(3, CHV_PPAT_SNOOP) |
+               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
+               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
+               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
+               GEN8_PPAT(7, CHV_PPAT_SNOOP);
+
+       vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
+
+       return 0;
+}
+
 static int guc_status_read(struct intel_vgpu *vgpu,
                           unsigned int offset, void *p_data,
                           unsigned int bytes)
@@ -2812,7 +2841,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
 
        MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
 
-       MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
+       MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
        MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
 
        MMIO_D(GAMTARBMODE, D_BDW_PLUS);
@@ -3140,7 +3169,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
                 NULL, NULL);
 
        MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
+       MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
 
        return 0;
 }
@@ -3314,9 +3343,21 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
        MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
        MMIO_D(GEN6_GFXPAUSE, D_BXT);
        MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
+       MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+              0, 0, D_BXT, NULL, NULL);
+       MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+              0, 0, D_BXT, NULL, NULL);
+       MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+              0, 0, D_BXT, NULL, NULL);
+       MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+              0, 0, D_BXT, NULL, NULL);
 
        MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
 
+       MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
+
        return 0;
 }