Merge drm/drm-next into drm-intel-gt-next

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / i915 / gt / intel_workarounds.c

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2afb4f8..bf84efb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -771,11 +771,19 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 
        /* Wa_14014947963:dg2 */
        if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
-               IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+           IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
                wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
 
+       /* Wa_18018764978:dg2 */
+       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+           IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+               wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+
        /* Wa_15010599737:dg2 */
        wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
+
+       /* Wa_18019271663:dg2 */
+       wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
@@ -1752,7 +1760,8 @@ static void wa_list_apply(const struct i915_wa_list *wal)
 
        fw = wal_get_fw_for_rmw(uncore, wal);
 
-       spin_lock_irqsave(&uncore->lock, flags);
+       intel_gt_mcr_lock(gt, &flags);
+       spin_lock(&uncore->lock);
        intel_uncore_forcewake_get__locked(uncore, fw);
 
        for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
@@ -1781,7 +1790,8 @@ static void wa_list_apply(const struct i915_wa_list *wal)
        }
 
        intel_uncore_forcewake_put__locked(uncore, fw);
-       spin_unlock_irqrestore(&uncore->lock, flags);
+       spin_unlock(&uncore->lock);
+       intel_gt_mcr_unlock(gt, flags);
 }
 
 void intel_gt_apply_workarounds(struct intel_gt *gt)
@@ -1802,7 +1812,8 @@ static bool wa_list_verify(struct intel_gt *gt,
 
        fw = wal_get_fw_for_rmw(uncore, wal);
 
-       spin_lock_irqsave(&uncore->lock, flags);
+       intel_gt_mcr_lock(gt, &flags);
+       spin_lock(&uncore->lock);
        intel_uncore_forcewake_get__locked(uncore, fw);
 
        for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
@@ -1812,7 +1823,8 @@ static bool wa_list_verify(struct intel_gt *gt,
                                wal->name, from);
 
        intel_uncore_forcewake_put__locked(uncore, fw);
-       spin_unlock_irqrestore(&uncore->lock, flags);
+       spin_unlock(&uncore->lock);
+       intel_gt_mcr_unlock(gt, flags);
 
        return ok;
 }
@@ -2895,25 +2907,12 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
        if (IS_PONTEVECCHIO(i915)) {
                wa_write(wal, XEHPC_L3SCRUB,
                         SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+               wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
        }
 
        if (IS_DG2(i915)) {
                wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
                wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
-
-               /*
-                * This is also listed as Wa_22012654132 for certain DG2
-                * steppings, but the tuning setting programming is a superset
-                * since it applies to all DG2 variants and steppings.
-                *
-                * Note that register 0xE420 is write-only and cannot be read
-                * back for verification on DG2 (due to Wa_14012342262), so
-                * we need to explicitly skip the readback.
-                */
-               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
-                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
-                          0 /* write-only, so skip validation */,
-                          true);
        }
 
        /*
@@ -2924,6 +2923,9 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
        if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
                wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
                                        THREAD_EX_ARB_MODE_RR_AFTER_DEP);
+
+       if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+               wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
 }
 
 /*
@@ -3006,6 +3008,19 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                /* Wa_18017747507:dg2 */
                wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
        }
+
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915))
+               /*
+                * Wa_22012654132
+                *
+                * Note that register 0xE420 is write-only and cannot be read
+                * back for verification on DG2 (due to Wa_14012342262), so
+                * we need to explicitly skip the readback.
+                */
+               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+                          0 /* write-only, so skip validation */,
+                          true);
 }
 
 static void