Merge drm/drm-next into drm-intel-next

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / i915 / gt / intel_workarounds.c

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 53f7838..8c0c050 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1313,7 +1313,7 @@ bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
 }
 
 __maybe_unused
-static inline bool is_nonpriv_flags_valid(u32 flags)
+static bool is_nonpriv_flags_valid(u32 flags)
 {
        /* Check only valid flag bits are set */
        if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
@@ -1850,6 +1850,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_write_or(wal,
                            GEN8_L3SQCREG4,
                            GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+               /* Disable atomics in L3 to prevent unrecoverable hangs */
+               wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
+                                GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+               wa_write_clr_set(wal, GEN8_L3SQCREG4,
+                                GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+               wa_write_clr_set(wal, GEN9_SCRATCH1,
+                                EVICTION_PERF_FIX_ENABLE, 0);
        }
 
        if (IS_HASWELL(i915)) {