drm/amd/display: Reduce delay when sink device not able to ACK 00340h write

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / amd / display / dc / core / dc_link.c

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9058e45..f68a0d9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -541,6 +541,7 @@ static void link_disconnect_sink(struct dc_link *link)
        }
 
        link->dpcd_sink_count = 0;
+       //link->dpcd_caps.dpcd_rev.raw = 0;
 }
 
 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
@@ -742,6 +743,7 @@ static bool detect_dp(struct dc_link *link,
                                                                sink_caps,
                                                                audio_support);
                link->dpcd_caps.dongle_type = sink_caps->dongle_type;
+               link->dpcd_caps.dpcd_rev.raw = 0;
        }
 
        return true;
@@ -821,7 +823,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
 {
        struct dc_sink_init_data sink_init_data = { 0 };
        struct display_sink_capability sink_caps = { 0 };
-       uint8_t i;
+       uint32_t i;
        bool converter_disable_audio = false;
        struct audio_support *aud_support = &link->dc->res_pool->audio_support;
        bool same_edid = false;
@@ -1663,6 +1665,12 @@ struct dc_link *link_create(const struct link_init_data *init_params)
        if (false == dc_link_construct(link, init_params))
                goto construct_fail;
 
+       /*
+        * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
+        * since struct preferred_link_setting won't be reset after S3.
+        */
+       link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
+
        return link;
 
 construct_fail:
@@ -2661,7 +2669,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
                return false;
 
        link->psr_settings.psr_allow_active = allow_active;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (!allow_active)
                dc_z10_restore(dc);
 #endif
@@ -2842,7 +2850,7 @@ bool dc_link_setup_psr(struct dc_link *link,
        psr_context->psr_level.u32all = 0;
 
        /*skip power down the single pipe since it blocks the cstate*/
-#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
                psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
                if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
@@ -3191,7 +3199,7 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
                /*stream_enc_inst*/
                config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
                config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
                config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
                config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
                config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;