Merge tag 'drm-next-5.6-2019-12-11' of git://people.freedesktop.org/~agd5f/linux...

[platform/kernel/linux-rpi.git] / drivers / gpu / drm / amd / amdgpu / cik.c

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 1dfe4a1..e9822ea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1461,7 +1461,6 @@ static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
 {
        struct pci_dev *root = adev->pdev->bus->self;
-       int bridge_pos, gpu_pos;
        u32 speed_cntl, current_data_rate;
        int i;
        u16 tmp16;
@@ -1496,12 +1495,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
                DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
        }
 
-       bridge_pos = pci_pcie_cap(root);
-       if (!bridge_pos)
-               return;
-
-       gpu_pos = pci_pcie_cap(adev->pdev);
-       if (!gpu_pos)
+       if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
                return;
 
        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@@ -1511,14 +1505,17 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
                        u16 bridge_cfg2, gpu_cfg2;
                        u32 max_lw, current_lw, tmp;
 
-                       pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
-                       pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
+                       pcie_capability_read_word(root, PCI_EXP_LNKCTL,
+                                                 &bridge_cfg);
+                       pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
+                                                 &gpu_cfg);
 
                        tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
-                       pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
+                       pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
 
                        tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
-                       pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
+                       pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
+                                                  tmp16);
 
                        tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
                        max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@@ -1542,15 +1539,23 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
 
                        for (i = 0; i < 10; i++) {
                                /* check status */
-                               pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
+                               pcie_capability_read_word(adev->pdev,
+                                                         PCI_EXP_DEVSTA,
+                                                         &tmp16);
                                if (tmp16 & PCI_EXP_DEVSTA_TRPND)
                                        break;
 
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
-                               pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL,
+                                                         &bridge_cfg);
+                               pcie_capability_read_word(adev->pdev,
+                                                         PCI_EXP_LNKCTL,
+                                                         &gpu_cfg);
 
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
-                               pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
+                                                         &bridge_cfg2);
+                               pcie_capability_read_word(adev->pdev,
+                                                         PCI_EXP_LNKCTL2,
+                                                         &gpu_cfg2);
 
                                tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
                                tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1563,26 +1568,45 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
                                msleep(100);
 
                                /* linkctl */
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL,
+                                                         &tmp16);
                                tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
                                tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
-                               pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
+                               pcie_capability_write_word(root, PCI_EXP_LNKCTL,
+                                                          tmp16);
 
-                               pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
+                               pcie_capability_read_word(adev->pdev,
+                                                         PCI_EXP_LNKCTL,
+                                                         &tmp16);
                                tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
                                tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
-                               pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
+                               pcie_capability_write_word(adev->pdev,
+                                                          PCI_EXP_LNKCTL,
+                                                          tmp16);
 
                                /* linkctl2 */
-                               pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
-                               pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
-
-                               pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
-                               pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
+                               pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
+                                                         &tmp16);
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (bridge_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
+                               pcie_capability_write_word(root,
+                                                          PCI_EXP_LNKCTL2,
+                                                          tmp16);
+
+                               pcie_capability_read_word(adev->pdev,
+                                                         PCI_EXP_LNKCTL2,
+                                                         &tmp16);
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (gpu_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
+                               pcie_capability_write_word(adev->pdev,
+                                                          PCI_EXP_LNKCTL2,
+                                                          tmp16);
 
                                tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
                                tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1597,15 +1621,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
        speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
        WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
 
-       pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~0xf;
+       pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
+       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
+
        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-               tmp16 |= 3; /* gen3 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-               tmp16 |= 2; /* gen2 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
-               tmp16 |= 1; /* gen1 */
-       pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
+       pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
 
        speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
        speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;