drm/amdgpu: track MQD size for gfx and compute

[platform/kernel/linux-starfive.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 3989e75..b0dc0a0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -27,6 +27,7 @@
 #include <drm/amdgpu_drm.h>
 #include <drm/gpu_scheduler.h>
 #include <drm/drm_print.h>
+#include <drm/drm_suballoc.h>
 
 struct amdgpu_device;
 struct amdgpu_ring;
@@ -92,7 +93,7 @@ enum amdgpu_ib_pool_type {
 };
 
 struct amdgpu_ib {
-       struct amdgpu_sa_bo             *sa_bo;
+       struct drm_suballoc             *sa_bo;
        uint32_t                        length_dw;
        uint64_t                        gpu_addr;
        uint32_t                        *ptr;
@@ -164,7 +165,6 @@ struct amdgpu_ring_funcs {
        bool                    support_64bit_ptrs;
        bool                    no_user_fence;
        bool                    secure_submission_supported;
-       unsigned                vmhub;
        unsigned                extra_dw;
 
        /* ring read/write ptr handling */
@@ -212,6 +212,8 @@ struct amdgpu_ring_funcs {
        void (*end_use)(struct amdgpu_ring *ring);
        void (*emit_switch_buffer) (struct amdgpu_ring *ring);
        void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+       void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
+                               u64 gds_va, bool init_shadow, int vmid);
        void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
                          uint32_t reg_val_offs);
        void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
@@ -249,12 +251,14 @@ struct amdgpu_ring {
        uint64_t                ptr_mask;
        uint32_t                buf_mask;
        u32                     idx;
+       u32                     xcc_id;
        u32                     me;
        u32                     pipe;
        u32                     queue;
        struct amdgpu_bo        *mqd_obj;
        uint64_t                mqd_gpu_addr;
        void                    *mqd_ptr;
+       unsigned                mqd_size;
        uint64_t                eop_gpu_addr;
        u32                     doorbell_index;
        bool                    use_doorbell;
@@ -274,6 +278,7 @@ struct amdgpu_ring {
        unsigned                cond_exe_offs;
        u64                     cond_exe_gpu_addr;
        volatile u32            *cond_exe_cpu_addr;
+       unsigned                vm_hub;
        unsigned                vm_inv_eng;
        struct dma_fence        *vmid_wait;
        bool                    has_compute_vm_bug;
@@ -307,6 +312,7 @@ struct amdgpu_ring {
 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
+#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
@@ -317,6 +323,7 @@ struct amdgpu_ring {
 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
 
+unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
 void amdgpu_ring_ib_end(struct amdgpu_ring *ring);