* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_GPIO
+
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
-#include <asm/arch/gpio.h>
+#include <log.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>
-#define MODE_BITS(gpio_pin) (gpio_pin * 2)
+#include "stm32_gpio_priv.h"
+
+#define STM32_GPIOS_PER_BANK 16
+
+#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
#define MODE_BITS_MASK 3
-#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
+#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
+
+#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
+#define PUPD_MASK 3
+
+#define OTYPE_BITS(gpio_pin) (gpio_pin)
+#define OTYPE_MSK 1
+
+static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
+ int idx,
+ int mode)
+{
+ int bits_index;
+ int mask;
+
+ bits_index = MODE_BITS(idx);
+ mask = MODE_BITS_MASK << bits_index;
+
+ clrsetbits_le32(®s->moder, mask, mode << bits_index);
+}
+
+static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
+{
+ return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
+}
+
+static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
+ int idx,
+ enum stm32_gpio_otype otype)
+{
+ int bits;
+
+ bits = OTYPE_BITS(idx);
+ clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
+}
+
+static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
+ int idx)
+{
+ return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
+}
+
+static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
+ int idx,
+ enum stm32_gpio_pupd pupd)
+{
+ int bits;
+
+ bits = PUPD_BITS(idx);
+ clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
+}
+
+static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
+ int idx)
+{
+ return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
+}
/*
* convert gpio offset to gpio index taking into account gpio holes
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
return 0;
}
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
writel(BSRR_BIT(idx, value), ®s->bsrr);
return GPIOF_FUNC;
}
+static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
+ ulong flags)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int idx;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ if (flags & GPIOD_IS_OUT) {
+ bool value = flags & GPIOD_IS_OUT_ACTIVE;
+
+ if (flags & GPIOD_OPEN_DRAIN)
+ stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
+ else
+ stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
+
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
+ writel(BSRR_BIT(idx, value), ®s->bsrr);
+
+ } else if (flags & GPIOD_IS_IN) {
+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
+ }
+ if (flags & GPIOD_PULL_UP)
+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
+ else if (flags & GPIOD_PULL_DOWN)
+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
+
+ return 0;
+}
+
+static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
+ ulong *flagsp)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int idx;
+ ulong dir_flags = 0;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ switch (stm32_gpio_get_moder(regs, idx)) {
+ case STM32_GPIO_MODE_OUT:
+ dir_flags |= GPIOD_IS_OUT;
+ if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
+ dir_flags |= GPIOD_OPEN_DRAIN;
+ if (readl(®s->idr) & BIT(idx))
+ dir_flags |= GPIOD_IS_OUT_ACTIVE;
+ break;
+ case STM32_GPIO_MODE_IN:
+ dir_flags |= GPIOD_IS_IN;
+ break;
+ default:
+ break;
+ }
+ switch (stm32_gpio_get_pupd(regs, idx)) {
+ case STM32_GPIO_PUPD_UP:
+ dir_flags |= GPIOD_PULL_UP;
+ break;
+ case STM32_GPIO_PUPD_DOWN:
+ dir_flags |= GPIOD_PULL_DOWN;
+ break;
+ default:
+ break;
+ }
+ *flagsp = dir_flags;
+
+ return 0;
+}
+
static const struct dm_gpio_ops gpio_stm32_ops = {
.direction_input = stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.get_value = stm32_gpio_get_value,
.set_value = stm32_gpio_set_value,
.get_function = stm32_gpio_get_function,
+ .set_flags = stm32_gpio_set_flags,
+ .get_flags = stm32_gpio_get_flags,
};
static int gpio_stm32_probe(struct udevice *dev)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct ofnode_phandle_args args;
+ const char *name;
struct clk clk;
fdt_addr_t addr;
- int ret;
+ int ret, i;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
priv->regs = (struct stm32_gpio_regs *)addr;
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct ofnode_phandle_args args;
- const char *name;
- int i;
-
name = dev_read_string(dev, "st,bank-name");
if (!name)
return -EINVAL;
ret = dev_read_phandle_with_args(dev, "gpio-ranges",
NULL, 3, i, &args);
+ if (!ret && args.args_count < 3)
+ return -EINVAL;
+
if (ret == -ENOENT) {
uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
++i, &args);
+ if (!ret && args.args_count < 3)
+ return -EINVAL;
}
dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
dev_err(dev, "failed to enable clock\n");
return ret;
}
- debug("clock enabled for device %s\n", dev->name);
+ dev_dbg(dev, "clock enabled\n");
return 0;
}
.probe = gpio_stm32_probe,
.ops = &gpio_stm32_ops,
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
+ .priv_auto = sizeof(struct stm32_gpio_priv),
};
projects / platform / kernel / u-boot.git / blobdiff