* based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
*
* Copyright 2010 eXMeritus, A Boeing Company
+ * Copyright 2020-2021 NXP
*/
#include <common.h>
#include <dm.h>
#include <mapmem.h>
#include <asm/gpio.h>
-
-struct ccsr_gpio {
- u32 gpdir;
- u32 gpodr;
- u32 gpdat;
- u32 gpier;
- u32 gpimr;
- u32 gpicr;
-};
+#include <asm/io.h>
+#include <dm/of_access.h>
struct mpc8xxx_gpio_data {
/* The bank's register base in memory */
struct ccsr_gpio __iomem *base;
/* The address of the registers; used to identify the bank */
- ulong addr;
+ phys_addr_t addr;
/* The GPIO count of the bank */
uint gpio_count;
/* The GPDAT register cannot be used to determine the value of output
*/
u32 dat_shadow;
ulong type;
+ bool little_endian;
};
enum {
return (1U << (31 - (gpio)));
}
-static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask)
{
- return in_be32(&base->gpdat) & mask;
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (data->little_endian)
+ return in_le32(&data->base->gpdat) & mask;
+ else
+ return in_be32(&data->base->gpdat) & mask;
}
-static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask)
{
- return in_be32(&base->gpdir) & mask;
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (data->little_endian)
+ return in_le32(&data->base->gpdir) & mask;
+ else
+ return in_be32(&data->base->gpdir) & mask;
}
-static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask)
{
- return in_be32(&base->gpodr) & mask;
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (data->little_endian)
+ return in_le32(&data->base->gpodr) & mask;
+ else
+ return in_be32(&data->base->gpodr) & mask;
}
-static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32
gpios)
{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
/* GPODR register 1 -> open drain on */
- setbits_be32(&base->gpodr, gpios);
+ if (data->little_endian)
+ setbits_le32(&data->base->gpodr, gpios);
+ else
+ setbits_be32(&data->base->gpodr, gpios);
}
-static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
+static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev,
u32 gpios)
{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
/* GPODR register 0 -> open drain off (actively driven) */
- clrbits_be32(&base->gpodr, gpios);
+ if (data->little_endian)
+ clrbits_le32(&data->base->gpodr, gpios);
+ else
+ clrbits_be32(&data->base->gpodr, gpios);
}
static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
u32 mask = gpio_mask(gpio);
/* GPDIR register 0 -> input */
- clrbits_be32(&data->base->gpdir, mask);
+ if (data->little_endian)
+ clrbits_le32(&data->base->gpdir, mask);
+ else
+ clrbits_be32(&data->base->gpdir, mask);
return 0;
}
data->dat_shadow &= ~mask;
}
- gpdir = in_be32(&base->gpdir);
+ if (data->little_endian)
+ gpdir = in_le32(&base->gpdir);
+ else
+ gpdir = in_be32(&base->gpdir);
+
gpdir |= gpio_mask(gpio);
- out_be32(&base->gpdat, gpdir & data->dat_shadow);
- out_be32(&base->gpdir, gpdir);
+
+ if (data->little_endian) {
+ out_le32(&base->gpdat, gpdir & data->dat_shadow);
+ out_le32(&base->gpdir, gpdir);
+ } else {
+ out_be32(&base->gpdat, gpdir & data->dat_shadow);
+ out_be32(&base->gpdir, gpdir);
+ }
return 0;
}
{
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
- if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+ if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) {
/* Output -> use shadowed value */
return !!(data->dat_shadow & gpio_mask(gpio));
}
/* Input -> read value from GPDAT register */
- return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
-}
-
-static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
-{
- struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
-
- return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
-}
-
-static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
- int value)
-{
- struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
-
- if (value)
- mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
- else
- mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
-
- return 0;
+ return !!mpc8xxx_gpio_get_val(dev, gpio_mask(gpio));
}
static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
{
- struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
int dir;
- dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
+ dir = !!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio));
return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
+static int mpc8xxx_gpio_of_to_plat(struct udevice *dev)
{
- struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
- fdt_addr_t addr;
- u32 reg[2];
+ struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
- dev_read_u32_array(dev, "reg", reg, 2);
- addr = dev_translate_address(dev, reg);
+ if (dev_read_bool(dev, "little-endian"))
+ data->little_endian = true;
- plat->addr = addr;
- plat->size = reg[1];
+ plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
return 0;
}
#endif
-static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
+static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev)
{
struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
- struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
unsigned long size = plat->size;
ulong driver_data = dev_get_driver_data(dev);
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
char name[32], *str;
- mpc8xxx_gpio_platdata_to_priv(dev);
+ mpc8xxx_gpio_plat_to_priv(dev);
- snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+ snprintf(name, sizeof(name), "MPC@%.8llx",
+ (unsigned long long)data->addr);
str = strdup(name);
if (!str)
return -ENOMEM;
+ if (device_is_compatible(dev, "fsl,qoriq-gpio")) {
+ if (data->little_endian)
+ out_le32(&data->base->gpibe, 0xffffffff);
+ else
+ out_be32(&data->base->gpibe, 0xffffffff);
+ }
+
uc_priv->bank_name = str;
uc_priv->gpio_count = data->gpio_count;
.direction_output = mpc8xxx_gpio_direction_output,
.get_value = mpc8xxx_gpio_get_value,
.set_value = mpc8xxx_gpio_set_value,
- .get_open_drain = mpc8xxx_gpio_get_open_drain,
- .set_open_drain = mpc8xxx_gpio_set_open_drain,
.get_function = mpc8xxx_gpio_get_function,
};
.id = UCLASS_GPIO,
.ops = &gpio_mpc8xxx_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+ .of_to_plat = mpc8xxx_gpio_of_to_plat,
+ .plat_auto = sizeof(struct mpc8xxx_gpio_plat),
.of_match = mpc8xxx_gpio_ids,
#endif
.probe = mpc8xxx_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
+ .priv_auto = sizeof(struct mpc8xxx_gpio_data),
};