+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <log.h>
#include <pch.h>
#include <pci.h>
#include <asm/cpu.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
return 0;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_of_to_plat(struct udevice *dev)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+ struct ich6_bank_plat *plat = dev_get_plat(dev);
u32 gpiobase;
int offset;
int ret;
static int ich6_gpio_probe(struct udevice *dev)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+ struct ich6_bank_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
const void *prop;
bank->io_sel = plat->base_addr + 4;
bank->lvl = plat->base_addr + 8;
- prop = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"use-lvl-write-cache", NULL);
if (prop)
bank->use_lvl_write_cache = true;
.id = UCLASS_GPIO,
.of_match = intel_ich6_gpio_ids,
.ops = &gpio_ich6_ops,
- .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
+ .of_to_plat = gpio_ich6_of_to_plat,
.probe = ich6_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
- .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
+ .priv_auto = sizeof(struct ich6_bank_priv),
+ .plat_auto = sizeof(struct ich6_bank_plat),
};