global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / drivers / ddr / fsl / util.c

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 1a49b28..e49cf6e 100644 (file)
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -11,10 +9,16 @@
 #include <asm/fsl_law.h>
 #endif
 #include <div64.h>
+#include <linux/delay.h>
 
 #include <fsl_ddr.h>
 #include <fsl_immap.h>
+#include <log.h>
 #include <asm/io.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+       defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
 
 /* To avoid 64-bit full-divides, we factor this here */
 #define ULL_2E12 2000000000000ULL
@@ -30,19 +34,19 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
 
        switch (ctrl_num) {
        case 0:
-               ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
                break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
        case 1:
-               ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
        case 2:
-               ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
        case 3:
                ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                break;
@@ -72,10 +76,13 @@ unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
 
        /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
        unsigned long long rem, mclk_ps = ULL_2E12;
-
-       /* Now perform the big divide, the result fits in 32-bits */
-       rem = do_div(mclk_ps, data_rate);
-       result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+       if (data_rate) {
+               /* Now perform the big divide, the result fits in 32-bits */
+               rem = do_div(mclk_ps, data_rate);
+               result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+       } else {
+               result = 0;
+       }
 
        return result;
 }
@@ -140,7 +147,7 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
        if (set_ddr_laws(base, size, law_memctl) < 0) {
                printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
                        law_memctl);
-               return ;
+               return;
        }
        debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
                base, size, law_memctl);
@@ -174,28 +181,28 @@ u32 fsl_ddr_get_intl3r(void)
 void print_ddr_info(unsigned int start_ctrl)
 {
        struct ccsr_ddr __iomem *ddr =
-               (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+               (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
 
-#if    defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if    defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
        u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 #endif
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
        uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 #endif
        uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        int cas_lat;
 
-#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
        if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
            (start_ctrl == 1)) {
-               ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
+               ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR;
                sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        }
 #endif
-#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
        if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
            (start_ctrl == 2)) {
-               ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
+               ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR;
                sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        }
 #endif
@@ -248,7 +255,7 @@ void print_ddr_info(unsigned int start_ctrl)
        else
                puts(", ECC off)");
 
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 #ifdef CONFIG_E6500
        if (*mcintl3r & 0x80000000) {
                puts("\n");
@@ -270,7 +277,7 @@ void print_ddr_info(unsigned int start_ctrl)
        }
 #endif
 #endif
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
        if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
                puts("\n");
                puts("       DDR Controller Interleaving Mode: ");
@@ -339,26 +346,26 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 {
        unsigned int i;
        u32 ddrc_debug20;
-       u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
-       u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+       u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
+       u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
        struct ccsr_ddr __iomem *ddr;
 
        for (i = first_ctrl; i <= last_ctrl; i++) {
                switch (i) {
                case 0:
-                       ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+                       ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
                        break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
                case 1:
-                       ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+                       ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
                case 2:
-                       ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+                       ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
                case 3:
                        ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                        break;
@@ -388,7 +395,7 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 
 void remove_unused_controllers(fsl_ddr_info_t *info)
 {
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
        int i;
        u64 nodeid;
        void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);