Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / drivers / ddr / fsl / util.c

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 5d6b362..ad53658 100644 (file)
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -7,7 +7,9 @@
  */
 
 #include <common.h>
+#ifdef CONFIG_PPC
 #include <asm/fsl_law.h>
+#endif
 #include <div64.h>
 
 #include <fsl_ddr.h>
@@ -79,6 +81,7 @@ unsigned int mclk_to_picos(unsigned int mclk)
        return get_memory_clk_period_ps() * mclk;
 }
 
+#ifdef CONFIG_PPC
 void
 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
                           unsigned int law_memctl,
@@ -113,6 +116,7 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
                         unsigned int memctl_interleaved,
                         unsigned int ctrl_num);
+#endif
 
 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 {
@@ -142,21 +146,21 @@ void board_add_ram_info(int use_default)
        u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 #endif
 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-       uint32_t cs0_config = in_be32(&ddr->cs0_config);
+       uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 #endif
-       uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
+       uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        int cas_lat;
 
 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
        if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
                ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
-               sdram_cfg = in_be32(&ddr->sdram_cfg);
+               sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        }
 #endif
 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
        if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
                ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
-               sdram_cfg = in_be32(&ddr->sdram_cfg);
+               sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        }
 #endif
        puts(" (DDR");
@@ -184,8 +188,8 @@ void board_add_ram_info(int use_default)
                puts(", 64-bit");
 
        /* Calculate CAS latency based on timing cfg values */
-       cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
-       if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
+       cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
+       if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
                cas_lat += (8 << 1);
        printf(", CL=%d", cas_lat >> 1);
        if (cas_lat & 0x1)
@@ -224,6 +228,9 @@ void board_add_ram_info(int use_default)
                puts("       DDR Controller Interleaving Mode: ");
 
                switch ((cs0_config >> 24) & 0xf) {
+               case FSL_DDR_256B_INTERLEAVING:
+                       puts("256B");
+                       break;
                case FSL_DDR_CACHE_LINE_INTERLEAVING:
                        puts("cache line");
                        break;