Merge tag 'tpm-030822' of https://source.denx.de/u-boot/custodians/u-boot-tpm

[platform/kernel/u-boot.git] / drivers / ddr / fsl / Kconfig

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 5925fe9..22400a9 100644 (file)
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -10,6 +10,12 @@ config SYS_FSL_MMDC
        help
          Select Freescale Multi Mode DDR controller (MMDC).
 
+config SYS_FSL_DDR_EMU
+       bool
+       help
+         Specify emulator support for DDR. Some DDR features such as deskew
+         training are not available.
+
 if SYS_FSL_DDR || SYS_FSL_MMDC
 
 config SYS_FSL_DDR_BE
@@ -169,6 +175,20 @@ config ECC_INIT_VIA_DDRCONTROLLER
          Use the DDR controller to auto initialize memory.  If not enabled,
          the DMA controller is responsible for doing this.
 
+config SYS_DDR_RAW_TIMING
+       bool "Get DDR timing information from something other than SPD"
+       help
+         This is common with soldered DDR chips onboard without SPD. DDR raw
+         timing parameters are extracted from datasheet and hard-coded into
+         header files or board specific files.
+
+config SYS_FSL_DDR_INTLV_256B
+       bool "Enforce 256-byte interleave"
+       help
+         DDR controller interleaving on 256-byte. This is a special
+         interleaving mode, handled by Dickens for Freescale layerscape SoCs
+         with ARM core.
+
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
@@ -263,6 +283,20 @@ config SYS_OR7_PRELIM
        depends on SYS_BR7_PRELIM_BOOL
 endmenu
 
+if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
+       TARGET_P1020RDB_PD || TARGET_P2020RDB
+
+config COMMON_INIT_DDR
+       bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
+
+config SPL_COMMON_INIT_DDR
+       bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
+
+config TPL_COMMON_INIT_DDR
+       bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
+
+endif
+
 config SYS_FSL_ERRATUM_A008378
        bool