* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/err.h>
#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/clk.h>
+#include <linux/ioport.h>
#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/sh_timer.h>
-#include <linux/slab.h>
#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
+#include <linux/sh_timer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+enum sh_tmu_model {
+ SH_TMU,
+ SH_TMU_SH3,
+};
struct sh_tmu_device;
void __iomem *mapbase;
struct clk *clk;
+ enum sh_tmu_model model;
+
+ raw_spinlock_t lock; /* Protect the shared start/stop register */
+
struct sh_tmu_channel *channels;
unsigned int num_channels;
-};
-static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
+ bool has_clockevent;
+ bool has_clocksource;
+};
#define TSTR -1 /* shared register */
#define TCOR 0 /* channel register */
{
unsigned long offs;
- if (reg_nr == TSTR)
- return ioread8(ch->tmu->mapbase);
+ if (reg_nr == TSTR) {
+ switch (ch->tmu->model) {
+ case SH_TMU_SH3:
+ return ioread8(ch->tmu->mapbase + 2);
+ case SH_TMU:
+ return ioread8(ch->tmu->mapbase + 4);
+ }
+ }
offs = reg_nr << 2;
unsigned long offs;
if (reg_nr == TSTR) {
- iowrite8(value, ch->tmu->mapbase);
- return;
+ switch (ch->tmu->model) {
+ case SH_TMU_SH3:
+ return iowrite8(value, ch->tmu->mapbase + 2);
+ case SH_TMU:
+ return iowrite8(value, ch->tmu->mapbase + 4);
+ }
}
offs = reg_nr << 2;
unsigned long flags, value;
/* start stop register shared by multiple timer channels */
- raw_spin_lock_irqsave(&sh_tmu_lock, flags);
+ raw_spin_lock_irqsave(&ch->tmu->lock, flags);
value = sh_tmu_read(ch, TSTR);
if (start)
value &= ~(1 << ch->index);
sh_tmu_write(ch, TSTR, value);
- raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
+ raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
}
static int __sh_tmu_enable(struct sh_tmu_channel *ch)
}
static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
- const char *name, unsigned long rating)
+ const char *name)
{
struct clocksource *cs = &ch->cs;
cs->name = name;
- cs->rating = rating;
+ cs->rating = 200;
cs->read = sh_tmu_clocksource_read;
cs->enable = sh_tmu_clocksource_enable;
cs->disable = sh_tmu_clocksource_disable;
}
static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
- const char *name, unsigned long rating)
+ const char *name)
{
struct clock_event_device *ced = &ch->ced;
int ret;
ced->name = name;
ced->features = CLOCK_EVT_FEAT_PERIODIC;
ced->features |= CLOCK_EVT_FEAT_ONESHOT;
- ced->rating = rating;
+ ced->rating = 200;
ced->cpumask = cpumask_of(0);
ced->set_next_event = sh_tmu_clock_event_next;
ced->set_mode = sh_tmu_clock_event_mode;
}
static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
- unsigned long clockevent_rating,
- unsigned long clocksource_rating)
+ bool clockevent, bool clocksource)
{
- if (clockevent_rating)
- sh_tmu_register_clockevent(ch, name, clockevent_rating);
- else if (clocksource_rating)
- sh_tmu_register_clocksource(ch, name, clocksource_rating);
+ if (clockevent) {
+ ch->tmu->has_clockevent = true;
+ sh_tmu_register_clockevent(ch, name);
+ } else if (clocksource) {
+ ch->tmu->has_clocksource = true;
+ sh_tmu_register_clocksource(ch, name);
+ }
return 0;
}
-static int sh_tmu_channel_setup(struct sh_tmu_channel *ch,
+static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
+ bool clockevent, bool clocksource,
struct sh_tmu_device *tmu)
{
- struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
+ /* Skip unused channels. */
+ if (!clockevent && !clocksource)
+ return 0;
ch->tmu = tmu;
+ ch->index = index;
- /*
- * The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps channel
- * registers blocks at base + 2 + 12 * index, while all other variants
- * map them at base + 4 + 12 * index. We can compute the index by just
- * dividing by 12, the 2 bytes or 4 bytes offset being hidden by the
- * integer division.
- */
- ch->index = cfg->channel_offset / 12;
+ if (tmu->model == SH_TMU_SH3)
+ ch->base = tmu->mapbase + 4 + ch->index * 12;
+ else
+ ch->base = tmu->mapbase + 8 + ch->index * 12;
- ch->irq = platform_get_irq(tmu->pdev, 0);
+ ch->irq = platform_get_irq(tmu->pdev, index);
if (ch->irq < 0) {
dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
ch->index);
ch->enable_count = 0;
return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
- cfg->clockevent_rating,
- cfg->clocksource_rating);
+ clockevent, clocksource);
}
-static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
+static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
{
- struct sh_timer_config *cfg = pdev->dev.platform_data;
struct resource *res;
- void __iomem *base;
- int ret;
- ret = -ENXIO;
-
- tmu->pdev = pdev;
-
- if (!cfg) {
- dev_err(&tmu->pdev->dev, "missing platform data\n");
- goto err0;
- }
-
- platform_set_drvdata(pdev, tmu);
res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
- goto err0;
+ return -ENXIO;
}
- /*
- * Map memory, let base point to our channel and mapbase to the
- * start/stop shared register.
- */
- base = ioremap_nocache(res->start, resource_size(res));
- if (base == NULL) {
- dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
- goto err0;
+ tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
+ if (tmu->mapbase == NULL)
+ return -ENXIO;
+
+ return 0;
+}
+
+static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
+{
+ struct device_node *np = tmu->pdev->dev.of_node;
+
+ tmu->model = SH_TMU;
+ tmu->num_channels = 3;
+
+ of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
+
+ if (tmu->num_channels != 2 && tmu->num_channels != 3) {
+ dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
+ tmu->num_channels);
+ return -EINVAL;
}
- tmu->mapbase = base - cfg->channel_offset;
+ return 0;
+}
+
+static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
+{
+ unsigned int i;
+ int ret;
+
+ tmu->pdev = pdev;
+
+ raw_spin_lock_init(&tmu->lock);
+
+ if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
+ ret = sh_tmu_parse_dt(tmu);
+ if (ret < 0)
+ return ret;
+ } else if (pdev->dev.platform_data) {
+ const struct platform_device_id *id = pdev->id_entry;
+ struct sh_timer_config *cfg = pdev->dev.platform_data;
+
+ tmu->model = id->driver_data;
+ tmu->num_channels = hweight8(cfg->channels_mask);
+ } else {
+ dev_err(&tmu->pdev->dev, "missing platform data\n");
+ return -ENXIO;
+ }
- /* get hold of clock */
- tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
+ /* Get hold of clock. */
+ tmu->clk = clk_get(&tmu->pdev->dev, "fck");
if (IS_ERR(tmu->clk)) {
dev_err(&tmu->pdev->dev, "cannot get clock\n");
- ret = PTR_ERR(tmu->clk);
- goto err1;
+ return PTR_ERR(tmu->clk);
}
ret = clk_prepare(tmu->clk);
if (ret < 0)
- goto err2;
+ goto err_clk_put;
- tmu->channels = kzalloc(sizeof(*tmu->channels), GFP_KERNEL);
+ /* Map the memory resource. */
+ ret = sh_tmu_map_memory(tmu);
+ if (ret < 0) {
+ dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
+ goto err_clk_unprepare;
+ }
+
+ /* Allocate and setup the channels. */
+ tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
+ GFP_KERNEL);
if (tmu->channels == NULL) {
ret = -ENOMEM;
- goto err3;
+ goto err_unmap;
}
- tmu->num_channels = 1;
-
- tmu->channels[0].base = base;
+ /*
+ * Use the first channel as a clock event device and the second channel
+ * as a clock source.
+ */
+ for (i = 0; i < tmu->num_channels; ++i) {
+ ret = sh_tmu_channel_setup(&tmu->channels[i], i,
+ i == 0, i == 1, tmu);
+ if (ret < 0)
+ goto err_unmap;
+ }
- ret = sh_tmu_channel_setup(&tmu->channels[0], tmu);
- if (ret < 0)
- goto err3;
+ platform_set_drvdata(pdev, tmu);
return 0;
- err3:
+err_unmap:
kfree(tmu->channels);
+ iounmap(tmu->mapbase);
+err_clk_unprepare:
clk_unprepare(tmu->clk);
- err2:
+err_clk_put:
clk_put(tmu->clk);
- err1:
- iounmap(base);
- err0:
return ret;
}
static int sh_tmu_probe(struct platform_device *pdev)
{
struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
- struct sh_timer_config *cfg = pdev->dev.platform_data;
int ret;
if (!is_early_platform_device(pdev)) {
}
tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
- if (tmu == NULL) {
- dev_err(&pdev->dev, "failed to allocate driver data\n");
+ if (tmu == NULL)
return -ENOMEM;
- }
ret = sh_tmu_setup(tmu, pdev);
if (ret) {
return 0;
out:
- if (cfg->clockevent_rating || cfg->clocksource_rating)
+ if (tmu->has_clockevent || tmu->has_clocksource)
pm_runtime_irq_safe(&pdev->dev);
else
pm_runtime_idle(&pdev->dev);
return -EBUSY; /* cannot unregister clockevent and clocksource */
}
+static const struct platform_device_id sh_tmu_id_table[] = {
+ { "sh-tmu", SH_TMU },
+ { "sh-tmu-sh3", SH_TMU_SH3 },
+ { }
+};
+MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
+
+static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
+ { .compatible = "renesas,tmu" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
+
static struct platform_driver sh_tmu_device_driver = {
.probe = sh_tmu_probe,
.remove = sh_tmu_remove,
.driver = {
.name = "sh_tmu",
- }
+ .of_match_table = of_match_ptr(sh_tmu_of_table),
+ },
+ .id_table = sh_tmu_id_table,
};
static int __init sh_tmu_init(void)
projects / platform / adaptation / renesas_rcar / renesas_kernel.git / blobdiff