clk: uniphier: rework UniPhier clk driver

[platform/kernel/u-boot.git] / drivers / clk / uniphier / clk-uniphier-mio.c

diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index c1e7197..18e6856 100644 (file)
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -5,136 +5,81 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include <dm/device.h>
-
 #include "clk-uniphier.h"
 
-#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx)      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x20 + 0x200 * (ch),     \
-               .mask = 0x00000100,             \
-               .data = 0x00000100,             \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x110 + 0x200 * (ch),    \
-               .mask = 0x00000001,             \
-               .data = 0x00000001,             \
-       }
+#define UNIPHIER_MIO_CLK_SD_GATE(id, ch)                               \
+       UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8)
 
-#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx)      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00000000,             \
-               .rate = 44444444,               \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00010000,             \
-               .rate = 33333333,               \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00020000,             \
-               .rate = 50000000,               \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00020000,             \
-               .rate = 66666666,               \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00001000,             \
-               .rate = 100000000,              \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00001100,             \
-               .rate = 40000000,               \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00001200,             \
-               .rate = 25000000,               \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x30 + 0x200 * (ch),     \
-               .mask = 0x00031300,             \
-               .data = 0x00001300,             \
-               .rate = 22222222,               \
-       }
+#define UNIPHIER_MIO_CLK_USB2(id, ch)                                  \
+       UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28)
 
-#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx)     \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x20 + 0x200 * (ch),     \
-               .mask = 0x30000000,             \
-               .data = 0x30000000,             \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x110 + 0x200 * (ch),    \
-               .mask = 0x01000000,             \
-               .data = 0x01000000,             \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x114 + 0x200 * (ch),    \
-               .mask = 0x00000001,             \
-               .data = 0x00000001,             \
-       }
+#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch)                              \
+       UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29)
+
+#define UNIPHIER_MIO_CLK_DMAC(id)                                      \
+       UNIPHIER_CLK_GATE((id), 0x20, 25)
 
-#define UNIPHIER_MIO_CLK_GATE_DMAC(idx)                \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x20,                    \
-               .mask = 0x02000000,             \
-               .data = 0x02000000,             \
-       },                                      \
-       {                                       \
-               .index = (idx),                 \
-               .reg = 0x110,                   \
-               .mask = 0x00020000,             \
-               .data = 0x00020000,             \
+#define UNIPHIER_MIO_CLK_SD_MUX(_id, ch)                               \
+       {                                                               \
+               .id = (_id),                                            \
+               .nr_muxs = 8,                                           \
+               .reg = 0x30 + 0x200 * (ch),                             \
+               .masks = {                                              \
+                       0x00031000,                                     \
+                       0x00031000,                                     \
+                       0x00031000,                                     \
+                       0x00031000,                                     \
+                       0x00001300,                                     \
+                       0x00001300,                                     \
+                       0x00001300,                                     \
+                       0x00001300,                                     \
+               },                                                      \
+               .vals = {                                               \
+                       0x00000000,                                     \
+                       0x00010000,                                     \
+                       0x00020000,                                     \
+                       0x00030000,                                     \
+                       0x00001000,                                     \
+                       0x00001100,                                     \
+                       0x00001200,                                     \
+                       0x00001300,                                     \
+               },                                                      \
+               .rates = {                                              \
+                       44444444,                                       \
+                       33333333,                                       \
+                       50000000,                                       \
+                       66666666,                                       \
+                       100000000,                                      \
+                       40000000,                                       \
+                       25000000,                                       \
+                       22222222,                                       \
+               },                                                      \
        }
 
 static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
-       UNIPHIER_MIO_CLK_GATE_SD(0, 0),
-       UNIPHIER_MIO_CLK_GATE_SD(1, 1),
-       UNIPHIER_MIO_CLK_GATE_SD(2, 2),         /* for PH1-Pro4 only */
-       UNIPHIER_MIO_CLK_GATE_USB(0, 3),
-       UNIPHIER_MIO_CLK_GATE_USB(1, 4),
-       UNIPHIER_MIO_CLK_GATE_USB(2, 5),
-       UNIPHIER_MIO_CLK_GATE_DMAC(6),
-       UNIPHIER_MIO_CLK_GATE_USB(3, 7),        /* for PH1-sLD3 only */
+       UNIPHIER_MIO_CLK_SD_GATE(0, 0),
+       UNIPHIER_MIO_CLK_SD_GATE(1, 1),
+       UNIPHIER_MIO_CLK_SD_GATE(2, 2),         /* for PH1-Pro4 only */
+       UNIPHIER_MIO_CLK_DMAC(7),
+       UNIPHIER_MIO_CLK_USB2(8, 0),
+       UNIPHIER_MIO_CLK_USB2(9, 1),
+       UNIPHIER_MIO_CLK_USB2(10, 2),
+       UNIPHIER_MIO_CLK_USB2(11, 3),           /* for PH1-sLD3 only */
+       UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
+       UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
+       UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
+       UNIPHIER_MIO_CLK_USB2_PHY(15, 3),       /* for PH1-sLD3 only */
+       UNIPHIER_CLK_END
 };
 
-static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
-       UNIPHIER_MIO_CLK_RATE_SD(0, 0),
-       UNIPHIER_MIO_CLK_RATE_SD(1, 1),
-       UNIPHIER_MIO_CLK_RATE_SD(2, 2),         /* for PH1-Pro4 only */
+static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = {
+       UNIPHIER_MIO_CLK_SD_MUX(0, 0),
+       UNIPHIER_MIO_CLK_SD_MUX(1, 1),
+       UNIPHIER_MIO_CLK_SD_MUX(2, 2),          /* for PH1-Pro4 only */
+       UNIPHIER_CLK_END
 };
 
-const struct uniphier_clk_soc_data uniphier_mio_clk_data = {
+const struct uniphier_clk_data uniphier_mio_clk_data = {
        .gate = uniphier_mio_clk_gate,
-       .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
-       .rate = uniphier_mio_clk_rate,
-       .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
+       .mux = uniphier_mio_clk_mux,
 };