clk: sunxi: add gating support to PLL1

[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / clk / sunxi / clk-sunxi.c

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index bae5e32..eeb623b 100644 (file)
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_apb1_config = {
 };
 
 static const struct factors_data sun4i_pll1_data __initconst = {
+       .enable = 31,
        .table = &sun4i_pll1_config,
        .getter = sun4i_get_pll1_factors,
 };
 
 static const struct factors_data sun6i_a31_pll1_data __initconst = {
+       .enable = 31,
        .table = &sun6i_a31_pll1_config,
        .getter = sun6i_a31_get_pll1_factors,
 };