clk: sunxi: add gating support to PLL1

[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / clk / sunxi / clk-sunxi.c

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 98fec4e..eeb623b 100644 (file)
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -23,6 +23,9 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
+/* Maximum number of parents our clocks have */
+#define SUNXI_MAX_PARENTS      5
+
 /**
  * sun4i_osc_clk_setup() - Setup function for gatable oscillator
  */
@@ -261,7 +264,11 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
  * sunxi_factors_clk_setup() - Setup function for factor clocks
  */
 
+#define SUNXI_FACTORS_MUX_MASK 0x3
+
 struct factors_data {
+       int enable;
+       int mux;
        struct clk_factors_config *table;
        void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
 };
@@ -294,11 +301,13 @@ static struct clk_factors_config sun4i_apb1_config = {
 };
 
 static const struct factors_data sun4i_pll1_data __initconst = {
+       .enable = 31,
        .table = &sun4i_pll1_config,
        .getter = sun4i_get_pll1_factors,
 };
 
 static const struct factors_data sun6i_a31_pll1_data __initconst = {
+       .enable = 31,
        .table = &sun6i_a31_pll1_config,
        .getter = sun6i_a31_get_pll1_factors,
 };
@@ -312,16 +321,71 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
                                           struct factors_data *data)
 {
        struct clk *clk;
+       struct clk_factors *factors;
+       struct clk_gate *gate = NULL;
+       struct clk_mux *mux = NULL;
+       struct clk_hw *gate_hw = NULL;
+       struct clk_hw *mux_hw = NULL;
        const char *clk_name = node->name;
-       const char *parent;
+       const char *parents[SUNXI_MAX_PARENTS];
        void *reg;
+       int i = 0;
 
        reg = of_iomap(node, 0);
 
-       parent = of_clk_get_parent_name(node, 0);
+       /* if we have a mux, we will have >1 parents */
+       while (i < SUNXI_MAX_PARENTS &&
+              (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+               i++;
+
+       factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
+       if (!factors)
+               return;
+
+       /* Add a gate if this factor clock can be gated */
+       if (data->enable) {
+               gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+               if (!gate) {
+                       kfree(factors);
+                       return;
+               }
+
+               /* set up gate properties */
+               gate->reg = reg;
+               gate->bit_idx = data->enable;
+               gate->lock = &clk_lock;
+               gate_hw = &gate->hw;
+       }
+
+       /* Add a mux if this factor clock can be muxed */
+       if (data->mux) {
+               mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
+               if (!mux) {
+                       kfree(factors);
+                       kfree(gate);
+                       return;
+               }
+
+               /* set up gate properties */
+               mux->reg = reg;
+               mux->shift = data->mux;
+               mux->mask = SUNXI_FACTORS_MUX_MASK;
+               mux->lock = &clk_lock;
+               mux_hw = &mux->hw;
+       }
+
+       /* set up factors properties */
+       factors->reg = reg;
+       factors->config = data->table;
+       factors->get_factors = data->getter;
+       factors->lock = &clk_lock;
 
-       clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
-                                  data->table, data->getter, &clk_lock);
+       clk = clk_register_composite(NULL, clk_name,
+                       parents, i,
+                       mux_hw, &clk_mux_ops,
+                       &factors->hw, &clk_factors_ops,
+                       gate_hw, &clk_gate_ops,
+                       i ? 0 : CLK_IS_ROOT);
 
        if (!IS_ERR(clk)) {
                of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -358,13 +422,14 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
 {
        struct clk *clk;
        const char *clk_name = node->name;
-       const char *parents[5];
+       const char *parents[SUNXI_MAX_PARENTS];
        void *reg;
        int i = 0;
 
        reg = of_iomap(node, 0);
 
-       while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+       while (i < SUNXI_MAX_PARENTS &&
+              (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
                i++;
 
        clk = clk_register_mux(NULL, clk_name, parents, i,