clk: samsung: exynos4: do not define number of clocks in bindings

[platform/kernel/linux-starfive.git] / drivers / clk / samsung / clk-exynos4.c

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 4320725..4ec4122 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -135,6 +135,9 @@
 #define PWR_CTRL1_USE_CORE1_WFI                        (1 << 1)
 #define PWR_CTRL1_USE_CORE0_WFI                        (1 << 0)
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR                                        (CLK_DIV_CORE2 + 1)
+
 /* the exynos4 soc type */
 enum exynos4_soc {
        EXYNOS4210,
@@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct device_node *np,
        if (!reg_base)
                panic("%s: failed to map registers\n", __func__);
 
-       ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+       ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
        hws = ctx->clk_data.hws;
 
        samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,