Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index d9950c1..d822aca 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -9,12 +9,13 @@
 #include <dm.h>
 #include <dt-structs.h>
 #include <errno.h>
+#include <malloc.h>
 #include <mapmem.h>
 #include <syscon.h>
 #include <bitfield.h>
 #include <asm/io.h>
 #include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3399-cru.h>
@@ -418,7 +419,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
        return 0;
 }
 
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
                            enum apll_l_frequencies apll_l_freq)
 {
        u32 aclkm_div;
@@ -453,7 +454,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
                     atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 }
 
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
                            enum apll_b_frequencies apll_b_freq)
 {
        u32 aclkm_div;
@@ -505,7 +506,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
        ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
 
-static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
+static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 {
        u32 div, con;
 
@@ -542,7 +543,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
        return DIV_TO_RATE(GPLL_HZ, div);
 }
 
-static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 {
        int src_clk_div;
 
@@ -619,7 +620,7 @@ static const struct spi_clkreg spi_clkregs[] = {
                .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 };
 
-static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 {
        const struct spi_clkreg *spiclk = NULL;
        u32 div, val;
@@ -641,7 +642,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
        return DIV_TO_RATE(GPLL_HZ, div);
 }
 
-static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 {
        const struct spi_clkreg *spiclk = NULL;
        int src_clk_div;
@@ -668,7 +669,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
        return rk3399_spi_get_clk(cru, clk_id);
 }
 
-static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
+static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
 {
        struct pll_div vpll_config = {0};
        int aclk_vop = 198 * MHz;
@@ -712,7 +713,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
        return hz;
 }
 
-static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
+static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 {
        u32 div, con;
 
@@ -739,7 +740,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
                return DIV_TO_RATE(GPLL_HZ, div);
 }
 
-static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
+static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
                                ulong clk_id, ulong set_rate)
 {
        int src_clk_div;
@@ -792,7 +793,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
        return rk3399_mmc_get_clk(cru, clk_id);
 }
 
-static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
+static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
 {
        ulong ret;
 
@@ -817,7 +818,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
 }
 
 #define PMUSGRF_DDR_RGN_CON16 0xff330040
-static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
+static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
                                ulong set_rate)
 {
        struct pll_div dpll_cfg;
@@ -863,7 +864,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
        return set_rate;
 }
 
-static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 {
        u32 div, val;
 
@@ -874,7 +875,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
        return DIV_TO_RATE(OSC_HZ, div);
 }
 
-static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 {
        int src_clk_div;
 
@@ -993,6 +994,14 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
        case DCLK_VOP1:
                ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
                break;
+       case ACLK_VOP1:
+       case HCLK_VOP1:
+       case HCLK_SD:
+               /**
+                * assigned-clocks handling won't require for vopl, so
+                * return 0 to satisfy clk_set_defaults during device probe.
+                */
+               return 0;
        case SCLK_DDRCLK:
                ret = rk3399_ddr_set_clk(priv->cru, rate);
                break;
@@ -1062,53 +1071,16 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
        return -ENOENT;
 }
 
-static int rk3399_clk_enable(struct clk *clk)
-{
-       switch (clk->id) {
-       case HCLK_HOST0:
-       case HCLK_HOST0_ARB:
-       case HCLK_HOST1:
-       case HCLK_HOST1_ARB:
-               return 0;
-
-       case SCLK_MAC:
-       case SCLK_MAC_RX:
-       case SCLK_MAC_TX:
-       case SCLK_MACREF:
-       case SCLK_MACREF_OUT:
-       case ACLK_GMAC:
-       case PCLK_GMAC:
-               /* Required to successfully probe the Designware GMAC driver */
-               return 0;
-
-       case SCLK_USB3OTG0_REF:
-       case SCLK_USB3OTG1_REF:
-       case SCLK_USB3OTG0_SUSPEND:
-       case SCLK_USB3OTG1_SUSPEND:
-       case ACLK_USB3OTG0:
-       case ACLK_USB3OTG1:
-       case ACLK_USB3_RKSOC_AXI_PERF:
-       case ACLK_USB3:
-       case ACLK_USB3_GRF:
-               /* Required to successfully probe the Designware USB3 driver */
-               return 0;
-       }
-
-       debug("%s: unsupported clk %ld\n", __func__, clk->id);
-       return -ENOENT;
-}
-
 static struct clk_ops rk3399_clk_ops = {
        .get_rate = rk3399_clk_get_rate,
        .set_rate = rk3399_clk_set_rate,
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
        .set_parent = rk3399_clk_set_parent,
 #endif
-       .enable = rk3399_clk_enable,
 };
 
 #ifdef CONFIG_SPL_BUILD
-static void rkclk_init(struct rk3399_cru *cru)
+static void rkclk_init(struct rockchip_cru *cru)
 {
        u32 aclk_div;
        u32 hclk_div;
@@ -1225,15 +1197,15 @@ static int rk3399_clk_bind(struct udevice *dev)
                debug("Warning: No sysreset driver: ret=%d\n", ret);
        } else {
                priv = malloc(sizeof(struct sysreset_reg));
-               priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
+               priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
                                                    glb_srst_fst_value);
-               priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
+               priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
                                                    glb_srst_snd_value);
                sys_child->priv = priv;
        }
 
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
-       ret = offsetof(struct rk3399_cru, softrst_con[0]);
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+       ret = offsetof(struct rockchip_cru, softrst_con[0]);
        ret = rockchip_reset_bind(dev, ret, 21);
        if (ret)
                debug("Warning: software reset driver bind faile\n");