#endif
};
-struct rk3288_clk_priv {
- struct rk3288_grf *grf;
- struct rk3288_cru *cru;
- ulong rate;
-};
-
struct pll_div {
u32 nr;
u32 nf;
/* Keep divisors as low as possible to reduce jitter and power usage */
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
+#ifdef CONFIG_SPL_BUILD
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
-
-void *rockchip_get_cru(void)
-{
- struct rk3288_clk_priv *priv;
- struct udevice *dev;
- int ret;
-
- ret = rockchip_get_clk(&dev);
- if (ret)
- return ERR_PTR(ret);
-
- priv = dev_get_priv(dev);
-
- return priv->cru;
-}
+#endif
static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
switch (periph) {
case HCLK_EMMC:
+ case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDMMC:
+ case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[11]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
break;
case HCLK_SDIO0:
+ case SCLK_SDIO0:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
}
switch (periph) {
case HCLK_EMMC:
+ case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_PLL_MASK << EMMC_PLL_SHIFT |
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
(src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
+ case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_PLL_MASK << MMC0_PLL_SHIFT |
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
(src_clk_div - 1) << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO0:
+ case SCLK_SDIO0:
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO0:
+ case SCLK_EMMC:
+ case SCLK_SDMMC:
+ case SCLK_SDIO0:
new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
break;
case SCLK_SPI0:
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
switch (clk->id) {
+ case PLL_APLL:
+ /* We only support a fixed rate here */
+ if (rate != 1800000000)
+ return -EINVAL;
+ rk3288_clk_configure_cpu(priv->cru, priv->grf);
+ new_rate = rate;
+ break;
case CLK_DDR:
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
break;
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO0:
+ case SCLK_EMMC:
+ case SCLK_SDMMC:
+ case SCLK_SDIO0:
new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
break;
case SCLK_SPI0:
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
+ priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
#endif
return 0;