common: Drop linux/bitops.h from common header

[platform/kernel/u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 99698b1..15e3833 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -14,8 +14,10 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
+#include <log.h>
 #include <wait_bit.h>
 #include <asm/io.h>
+#include <linux/bitops.h>
 
 #include <dt-bindings/clock/renesas-cpg-mssr.h>
 
@@ -96,7 +98,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
                if (ret)
                        return ret;
 
-               if (core->type == CLK_TYPE_GEN3_PE) {
+               if (core->type == CLK_TYPE_GEN3_MDSEL) {
                        parent->dev = clk->dev;
                        parent->id = core->parent >> (priv->sscg ? 16 : 0);
                        parent->id &= 0xffff;
@@ -107,7 +109,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
        return renesas_clk_get_parent(clk, info, parent);
 }
 
-static int gen3_clk_setup_sdif_div(struct clk *clk)
+static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
 {
        struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
        struct cpg_mssr_info *info = priv->info;
@@ -133,7 +135,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
 
        debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
 
-       writel(1, priv->base + core->offset);
+       writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
 
        return 0;
 }
@@ -141,10 +143,6 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
 static int gen3_clk_enable(struct clk *clk)
 {
        struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
-       int ret = gen3_clk_setup_sdif_div(clk);
-
-       if (ret)
-               return ret;
 
        return renesas_clk_endisable(clk, priv->base, true);
 }
@@ -261,7 +259,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                      core->parent, core->mult, core->div, rate);
                return rate;
 
-       case CLK_TYPE_GEN3_PE:
+       case CLK_TYPE_GEN3_MDSEL:
                div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
                rate = gen3_clk_get_rate64(&parent) / div;
                debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
@@ -328,7 +326,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 {
        /* Force correct SD-IF divider configuration if applicable */
-       gen3_clk_setup_sdif_div(clk);
+       gen3_clk_setup_sdif_div(clk, rate);
        return gen3_clk_get_rate64(clk);
 }