common: Drop linux/bitops.h from common header

[platform/kernel/u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 834cd5a..15e3833 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -14,8 +14,10 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
+#include <log.h>
 #include <wait_bit.h>
 #include <asm/io.h>
+#include <linux/bitops.h>
 
 #include <dt-bindings/clock/renesas-cpg-mssr.h>
 
@@ -85,7 +87,29 @@ static const struct sd_div_table cpg_sd_div_table[] = {
        CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
 };
 
-static int gen3_clk_setup_sdif_div(struct clk *clk)
+static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
+                              struct cpg_mssr_info *info, struct clk *parent)
+{
+       const struct cpg_core_clk *core;
+       int ret;
+
+       if (!renesas_clk_is_mod(clk)) {
+               ret = renesas_clk_get_core(clk, info, &core);
+               if (ret)
+                       return ret;
+
+               if (core->type == CLK_TYPE_GEN3_MDSEL) {
+                       parent->dev = clk->dev;
+                       parent->id = core->parent >> (priv->sscg ? 16 : 0);
+                       parent->id &= 0xffff;
+                       return 0;
+               }
+       }
+
+       return renesas_clk_get_parent(clk, info, parent);
+}
+
+static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
 {
        struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
        struct cpg_mssr_info *info = priv->info;
@@ -93,7 +117,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
        struct clk parent;
        int ret;
 
-       ret = renesas_clk_get_parent(clk, info, &parent);
+       ret = gen3_clk_get_parent(priv, clk, info, &parent);
        if (ret) {
                printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
                return ret;
@@ -111,7 +135,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
 
        debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
 
-       writel(1, priv->base + core->offset);
+       writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
 
        return 0;
 }
@@ -119,10 +143,6 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
 static int gen3_clk_enable(struct clk *clk)
 {
        struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
-       int ret = gen3_clk_setup_sdif_div(clk);
-
-       if (ret)
-               return ret;
 
        return renesas_clk_endisable(clk, priv->base, true);
 }
@@ -142,13 +162,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
        const struct cpg_core_clk *core;
        const struct rcar_gen3_cpg_pll_config *pll_config =
                                        priv->cpg_pll_config;
-       u32 value, mult, prediv, postdiv;
+       u32 value, mult, div, prediv, postdiv;
        u64 rate = 0;
        int i, ret;
 
        debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 
-       ret = renesas_clk_get_parent(clk, info, &parent);
+       ret = gen3_clk_get_parent(priv, clk, info, &parent);
        if (ret) {
                printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
                return ret;
@@ -200,9 +220,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN3_PLL1:
                rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
-               debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n",
+               rate /= pll_config->pll1_div;
+               debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
                      __func__, __LINE__,
-                     core->parent, pll_config->pll1_mult, rate);
+                     core->parent, pll_config->pll1_mult,
+                     pll_config->pll1_div, rate);
                return rate;
 
        case CLK_TYPE_GEN3_PLL2:
@@ -215,9 +237,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN3_PLL3:
                rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
-               debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n",
+               rate /= pll_config->pll3_div;
+               debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
                      __func__, __LINE__,
-                     core->parent, pll_config->pll3_mult, rate);
+                     core->parent, pll_config->pll3_mult,
+                     pll_config->pll3_div, rate);
                return rate;
 
        case CLK_TYPE_GEN3_PLL4:
@@ -229,13 +253,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                return rate;
 
        case CLK_TYPE_FF:
-       case CLK_TYPE_GEN3_PE:          /* FIXME */
                rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
                debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
                      __func__, __LINE__,
                      core->parent, core->mult, core->div, rate);
                return rate;
 
+       case CLK_TYPE_GEN3_MDSEL:
+               div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
+               rate = gen3_clk_get_rate64(&parent) / div;
+               debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
+                     __func__, __LINE__,
+                     (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
+                     div, rate);
+               return rate;
+
        case CLK_TYPE_GEN3_SD:          /* FIXME */
                value = readl(priv->base + core->offset);
                value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
@@ -294,7 +326,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 {
        /* Force correct SD-IF divider configuration if applicable */
-       gen3_clk_setup_sdif_div(clk);
+       gen3_clk_setup_sdif_div(clk, rate);
        return gen3_clk_get_rate64(clk);
 }
 
@@ -347,6 +379,8 @@ int gen3_clk_probe(struct udevice *dev)
        if (!priv->cpg_pll_config->extal_div)
                return -EINVAL;
 
+       priv->sscg = !(cpg_mode & BIT(12));
+
        ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
        if (ret < 0)
                return ret;