#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
+#include <log.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <linux/bitops.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
if (ret)
return ret;
- if (core->type == CLK_TYPE_GEN3_PE) {
+ if (core->type == CLK_TYPE_GEN3_MDSEL) {
parent->dev = clk->dev;
parent->id = core->parent >> (priv->sscg ? 16 : 0);
parent->id &= 0xffff;
core->parent, core->mult, core->div, rate);
return rate;
- case CLK_TYPE_GEN3_PE:
+ case CLK_TYPE_GEN3_MDSEL:
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div;
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",