Merge tag 'u-boot-imx-20200825' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

[platform/kernel/u-boot.git] / drivers / clk / mediatek / clk-mt7622.c

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index a5b61a1..0246149 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -8,9 +8,11 @@
 
 #include <common.h>
 #include <dm.h>
+#include <log.h>
 #include <asm/arch-mediatek/reset.h>
 #include <asm/io.h>
 #include <dt-bindings/clock/mt7622-clk.h>
+#include <linux/bitops.h>
 
 #include "clk-mtk.h"
 
@@ -451,6 +453,41 @@ static const struct mtk_gate peri_cgs[] = {
        GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
 };
 
+/* pciesys */
+static const struct mtk_gate_regs pcie_cg_regs = {
+       .set_ofs = 0x30,
+       .clr_ofs = 0x30,
+       .sta_ofs = 0x30,
+};
+
+#define GATE_PCIE(_id, _parent, _shift) {              \
+               .id = _id,                              \
+               .parent = _parent,                      \
+               .regs = &pcie_cg_regs,                  \
+               .shift = _shift,                        \
+               .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
+       }
+
+static const struct mtk_gate pcie_cgs[] = {
+       GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12),
+       GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13),
+       GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
+       GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15),
+       GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16),
+       GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17),
+       GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
+       GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19),
+       GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
+       GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),
+       GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22),
+       GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23),
+       GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
+       GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27),
+       GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28),
+       GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29),
+       GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30),
+};
+
 /* ethsys */
 static const struct mtk_gate_regs eth_cg_regs = {
        .sta_ofs = 0x30,
@@ -484,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
        .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 }
 
+static const struct mtk_gate_regs ssusb_cg_regs = {
+       .set_ofs = 0x30,
+       .clr_ofs = 0x30,
+       .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) {                      \
+       .id = _id,                                              \
+       .parent = _parent,                                      \
+       .regs = &ssusb_cg_regs,                                 \
+       .shift = _shift,                                        \
+       .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
+}
+
 static const struct mtk_gate sgmii_cgs[] = {
        GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
        GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@@ -491,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
        GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
 };
 
+static const struct mtk_gate ssusb_cgs[] = {
+       GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+       GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+       GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+       GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+       GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+       GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
 static const struct mtk_clk_tree mt7622_clk_tree = {
        .xtal_rate = 25 * MHZ,
        .xtal2_rate = 25 * MHZ,
@@ -552,6 +612,24 @@ static int mt7622_pericfg_probe(struct udevice *dev)
        return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
 }
 
+static int mt7622_pciesys_probe(struct udevice *dev)
+{
+       return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
+}
+
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+       int ret = 0;
+
+       if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+       ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+       if (ret)
+               debug("Warning: failed to bind reset controller\n");
+       }
+
+       return ret;
+}
+
 static int mt7622_ethsys_probe(struct udevice *dev)
 {
        return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
@@ -575,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
        return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
 }
 
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+       return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
 static const struct udevice_id mt7622_apmixed_compat[] = {
        { .compatible = "mediatek,mt7622-apmixedsys" },
        { }
@@ -595,6 +678,11 @@ static const struct udevice_id mt7622_pericfg_compat[] = {
        { }
 };
 
+static const struct udevice_id mt7622_pciesys_compat[] = {
+       { .compatible = "mediatek,mt7622-pciesys", },
+       { }
+};
+
 static const struct udevice_id mt7622_ethsys_compat[] = {
        { .compatible = "mediatek,mt7622-ethsys", },
        { }
@@ -610,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
        { }
 };
 
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+       { .compatible = "mediatek,mt7622-ssusbsys" },
+       { }
+};
+
 U_BOOT_DRIVER(mtk_mcucfg) = {
        .name = "mt7622-mcucfg",
        .id = UCLASS_SYSCON,
@@ -658,6 +751,16 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
        .flags = DM_FLAG_PRE_RELOC,
 };
 
+U_BOOT_DRIVER(mtk_clk_pciesys) = {
+       .name = "mt7622-clock-pciesys",
+       .id = UCLASS_CLK,
+       .of_match = mt7622_pciesys_compat,
+       .probe = mt7622_pciesys_probe,
+       .bind = mt7622_pciesys_bind,
+       .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+       .ops = &mtk_clk_gate_ops,
+};
+
 U_BOOT_DRIVER(mtk_clk_ethsys) = {
        .name = "mt7622-clock-ethsys",
        .id = UCLASS_CLK,
@@ -676,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
        .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
        .ops = &mtk_clk_gate_ops,
 };
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+       .name = "mt7622-clock-ssusbsys",
+       .id = UCLASS_CLK,
+       .of_match = mt7622_ssusbsys_compat,
+       .probe = mt7622_ssusbsys_probe,
+       .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+       .ops = &mtk_clk_gate_ops,
+};