Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

[platform/kernel/u-boot.git] / drivers / clk / clk_zynq.c

diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index d647e0a..e80500e 100644 (file)
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -10,6 +10,9 @@
 #include <common.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
 #include <dm/lists.h>
 #include <errno.h>
 #include <asm/io.h>
@@ -434,17 +437,29 @@ static ulong zynq_clk_get_rate(struct clk *clk)
        case lqspi_clk ... pcap_clk:
        case sdio0_clk ... spi1_clk:
                return zynq_clk_get_peripheral_rate(priv, id, 0);
+       case i2c0_aper_clk ... i2c1_aper_clk:
+               return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
        default:
                return -ENXIO;
        }
 }
 #endif
 
+static int dummy_enable(struct clk *clk)
+{
+       /*
+        * Add implementation but by default all clocks are enabled
+        * after power up which is only one supported case now.
+        */
+       return 0;
+}
+
 static struct clk_ops zynq_clk_ops = {
        .get_rate = zynq_clk_get_rate,
 #ifndef CONFIG_SPL_BUILD
        .set_rate = zynq_clk_set_rate,
 #endif
+       .enable = dummy_enable,
 };
 
 static int zynq_clk_probe(struct udevice *dev)
@@ -457,8 +472,9 @@ static int zynq_clk_probe(struct udevice *dev)
 
        for (i = 0; i < 2; i++) {
                sprintf(name, "gem%d_emio_clk", i);
-               ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]);
-               if (ret < 0 && ret != -ENODATA) {
+               ret = clk_get_by_name_optional(dev, name,
+                                              &priv->gem_emio_clk[i]);
+               if (ret) {
                        dev_err(dev, "failed to get %s clock\n", name);
                        return ret;
                }
@@ -480,8 +496,7 @@ U_BOOT_DRIVER(zynq_clk) = {
        .name           = "zynq_clk",
        .id             = UCLASS_CLK,
        .of_match       = zynq_clk_ids,
-       .flags          = DM_FLAG_PRE_RELOC,
        .ops            = &zynq_clk_ops,
-       .priv_auto_alloc_size = sizeof(struct zynq_clk_priv),
+       .priv_auto      = sizeof(struct zynq_clk_priv),
        .probe          = zynq_clk_probe,
 };