+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
*
* Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
#include <dm/lists.h>
#include <errno.h>
#include <asm/io.h>
return zynq_clk_get_peripheral_rate(priv, id, two_divs);
case dma_clk:
return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
- case usb0_aper_clk ... smc_aper_clk:
+ case usb0_aper_clk ... swdt_clk:
return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
default:
return -ENXIO;
case lqspi_clk ... pcap_clk:
case sdio0_clk ... spi1_clk:
return zynq_clk_get_peripheral_rate(priv, id, 0);
+ case i2c0_aper_clk ... i2c1_aper_clk:
+ return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
default:
return -ENXIO;
}
}
#endif
+static int dummy_enable(struct clk *clk)
+{
+ /*
+ * Add implementation but by default all clocks are enabled
+ * after power up which is only one supported case now.
+ */
+ return 0;
+}
+
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
.set_rate = zynq_clk_set_rate,
#endif
+ .enable = dummy_enable,
};
static int zynq_clk_probe(struct udevice *dev)
for (i = 0; i < 2; i++) {
sprintf(name, "gem%d_emio_clk", i);
- ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]);
- if (ret < 0 && ret != -FDT_ERR_NOTFOUND) {
+ ret = clk_get_by_name_optional(dev, name,
+ &priv->gem_emio_clk[i]);
+ if (ret) {
dev_err(dev, "failed to get %s clock\n", name);
return ret;
}
.name = "zynq_clk",
.id = UCLASS_CLK,
.of_match = zynq_clk_ids,
- .flags = DM_FLAG_PRE_RELOC,
.ops = &zynq_clk_ops,
- .priv_auto_alloc_size = sizeof(struct zynq_clk_priv),
+ .priv_auto = sizeof(struct zynq_clk_priv),
.probe = zynq_clk_probe,
};