*/
#include <common.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include <malloc.h>
#include <dm.h>
#include <asm/arch/sys_proto.h>
#include <zynqmp_firmware.h>
+#include <linux/err.h>
#define MAX_PARENT 100
#define MAX_NODES 6
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 div;
- versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
div = ret_payload[1];
return div;
{
u32 ret_payload[PAYLOAD_ARG_CNT];
- versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
return div;
}
u32 ret_payload[PAYLOAD_ARG_CNT];
int ref;
- versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
ref = ret_payload[0];
if (!(ref & 1))
return ref_clk;
u32 parent_rate, parent_id;
u32 id = clk_id & 0xFFF;
- versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
res = ret_payload[1];
if (!res) {
printf("0%x PLL not enabled\n", clk_id);
parent_id = clock[clock[id].parent[0].id].clk_id;
parent_rate = versal_clock_ref(parent_id);
- versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
fbdiv = ret_payload[1];
- versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+ xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
frac = ret_payload[1];
freq = (fbdiv * parent_rate) >> (1 << frac);
u32 id = clk_id & 0xFFF;
if (versal_clock_mux(clk_id)) {
- versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+ xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
ret_payload);
parent_id = ret_payload[1];
}
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
return versal_clock_ref(clk_id);
+ if (!parent_id)
+ return 0;
+
clk_rate = versal_clock_calc(parent_id);
if (versal_clock_div(clk_id)) {
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
((clk_id >> NODE_CLASS_SHIFT) &
NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
- if (!versal_clock_gate(clk_id))
+ if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
return -EINVAL;
*clk_rate = versal_clock_calc(clk_id);
return 0;
continue;
clock[i].valid = attr & CLK_VALID_MASK;
+
+ /* skip query for Invalid clock */
+ ret = versal_is_valid_clock(i);
+ if (ret != CLK_VALID_MASK)
+ continue;
+
clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;