#define RCC_FMCCKSELR 0x904
#define RCC_USBCKSELR 0x91C
#define RCC_DSICKSELR 0x924
+#define RCC_ADCCKSELR 0x928
#define RCC_MP_APB1ENSETR 0xA00
#define RCC_MP_APB2ENSETR 0XA08
#define RCC_MP_APB3ENSETR 0xA10
#define RCC_MP_AHB2ENSETR 0xA18
+#define RCC_MP_AHB3ENSETR 0xA20
#define RCC_MP_AHB4ENSETR 0xA28
/* used for most of SELR register */
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_DIGBYP BIT(7)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
_USBO_SEL,
_STGEN_SEL,
_DSI_SEL,
+ _ADC12_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
+
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
+static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
[_USBO_SEL] = "USBO",
[_STGEN_SEL] = "STGEN",
[_DSI_SEL] = "DSI",
+ [_ADC12_SEL] = "ADC12",
};
#endif
return ret;
}
-static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
+ int lsedrv)
{
u32 value;
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
+
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
/*
stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
}
-static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
{
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP);
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass;
- int lsedrv;
+ int bypass, digbyp, lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
lse_css = dev_read_bool(dev, "st,css");
lsedrv = dev_read_u32_default(dev, "st,drive",
LSEDRV_MEDIUM_HIGH);
- stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
}
if (priv->osc[_HSE]) {
- int bypass, css;
+ int bypass, digbyp, css;
struct udevice *dev = priv->osc_dev[_HSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
css = dev_read_bool(dev, "st,css");
- stm32mp1_hse_enable(rcc, bypass, css);
+ stm32mp1_hse_enable(rcc, bypass, digbyp, css);
}
/* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
* => switch on CSI even if node is not present in device tree