* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <div64.h>
#include <dm.h>
+#include <init.h>
+#include <log.h>
#include <regmap.h>
#include <spl.h>
#include <syscon.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
+#include <time.h>
+#include <vsprintf.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_STM32MP1_TRUSTED
+#ifndef CONFIG_TFABOOT
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* activate clock tree initialization in the driver */
#define STM32MP1_CLOCK_TREE_INIT
#define RCC_PLL4CSGR 0x8A4
#define RCC_I2C12CKSELR 0x8C0
#define RCC_I2C35CKSELR 0x8C4
+#define RCC_SPI2S1CKSELR 0x8D8
+#define RCC_SPI45CKSELR 0x8E0
#define RCC_UART6CKSELR 0x8E4
#define RCC_UART24CKSELR 0x8E8
#define RCC_UART35CKSELR 0x8EC
_STGEN_SEL,
_DSI_SEL,
_ADC12_SEL,
+ _SPI1_SEL,
+ _SPI45_SEL,
+ _RTC_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
+
+ STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
};
static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
+static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
+ _PLL3_R};
+static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
sdmmc3_parents),
STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
- STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
- STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
+ STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
+ STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
- STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
+ STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
+ STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
+ STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
+ (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
+ rtc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
+
/* define characteristic of PLL according type */
+#define DIVM_MIN 0
+#define DIVM_MAX 63
#define DIVN_MIN 24
+#define DIVP_MIN 0
+#define DIVP_MAX 127
+#define FRAC_MAX 8192
+
+#define PLL1600_VCO_MIN 800000000
+#define PLL1600_VCO_MAX 1600000000
+
static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
[PLL_800] = {
.refclk_min = 4,
[_STGEN_SEL] = "STGEN",
[_DSI_SEL] = "DSI",
[_ADC12_SEL] = "ADC12",
+ [_SPI1_SEL] = "SPI1",
+ [_SPI45_SEL] = "SPI45",
+ [_RTC_SEL] = "RTC",
};
static const struct stm32mp1_clk_data stm32mp1_data = {
static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
{
if (idx >= NB_OSC) {
- debug("%s: clk id %d not found\n", __func__, idx);
+ log_debug("clk id %d not found\n", idx);
return 0;
}
- debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
- (u32)priv->osc[idx], priv->osc[idx] / 1000);
-
return priv->osc[idx];
}
}
if (i == nb_clks) {
- printf("%s: clk id %d not found\n", __func__, (u32)id);
+ log_err("clk id %d not found\n", (u32)id);
return -EINVAL;
}
const struct stm32mp1_clk_gate *gate = priv->data->gate;
if (gate[i].sel > _PARENT_SEL_NB) {
- printf("%s: parents for clk id %d not found\n",
- __func__, i);
+ log_err("parents for clk id %d not found\n", i);
return -EINVAL;
}
const struct stm32mp1_clk_sel *sel = priv->data->sel;
int i;
int s, p;
+ unsigned int idx;
- for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
- if (stm32mp1_clks[i][0] == id)
- return stm32mp1_clks[i][1];
+ for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
+ if (stm32mp1_clks[idx][0] == id)
+ return stm32mp1_clks[idx][1];
i = stm32mp1_clk_get_id(priv, id);
if (i < 0)
p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
if (p < sel[s].nb_parent) {
-#ifdef DEBUG
- debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
- stm32mp1_clk_parent_name[sel[s].parent[p]],
- stm32mp1_clk_parent_sel_name[s],
- (u32)id);
-#endif
+ log_content("%s clock is the parent %s of clk id %d\n",
+ stm32mp1_clk_parent_name[sel[s].parent[p]],
+ stm32mp1_clk_parent_sel_name[s],
+ (u32)id);
return sel[s].parent[p];
}
- pr_err("%s: no parents defined for clk id %d\n",
- __func__, (u32)id);
+ log_err("no parents defined for clk id %d\n", (u32)id);
return -EINVAL;
}
src = selr & RCC_SELR_SRC_MASK;
refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
- debug("PLL%d : selr=%x refclk = %d kHz\n",
- pll_id, selr, (u32)(refclk / 1000));
return refclk;
}
divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
- debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
- pll_id, cfgr1, fracr, divn, divm);
-
refclk = pll_get_fref_ck(priv, pll_id);
/* with FRACV :
} else {
fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
}
- debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
return fvco;
}
ulong dfout;
u32 cfgr2;
- debug("%s(%d, %d)\n", __func__, pll_id, div_id);
if (div_id >= _DIV_NB)
return 0;
cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
- debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
-
dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
- debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
return dfout;
}
case RCC_MPCKSELR_PLL:
case RCC_MPCKSELR_PLL_MPUDIV:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
- if (p == RCC_MPCKSELR_PLL_MPUDIV) {
+ if ((reg & RCC_SELR_SRC_MASK) ==
+ RCC_MPCKSELR_PLL_MPUDIV) {
reg = readl(priv->base + RCC_MPCKDIVR);
- clock /= stm32mp1_mpu_div[reg &
- RCC_MPUDIV_MASK];
+ clock >>= stm32mp1_mpu_div[reg &
+ RCC_MPUDIV_MASK];
}
break;
}
if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
&dev)) {
if (clk_request(dev, &clk)) {
- pr_err("ck_dsi_phy request");
+ log_err("ck_dsi_phy request");
} else {
clk.id = 0;
clock = clk_get_rate(&clk);
break;
}
- debug("%s(%d) clock = %lx : %ld kHz\n",
- __func__, p, clock, clock / 1000);
+ log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
return clock;
}
else
setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
- debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
+ dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
return 0;
}
else
clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
- debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
+ dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
return 0;
}
rate = stm32mp1_clk_get(priv, p);
-#ifdef DEBUG
- debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
- __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
-#endif
+ dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
+ (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
+
return rate;
}
#ifdef STM32MP1_CLOCK_TREE_INIT
+
+bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
+{
+ unsigned int id;
+
+ switch (opp_id) {
+ case 1:
+ case 2:
+ id = opp_id;
+ break;
+ default:
+ id = 1; /* default value */
+ break;
+ }
+
+ switch (cpu_type) {
+ case CPU_STM32MP157Fxx:
+ case CPU_STM32MP157Dxx:
+ case CPU_STM32MP153Fxx:
+ case CPU_STM32MP153Dxx:
+ case CPU_STM32MP151Fxx:
+ case CPU_STM32MP151Dxx:
+ return true;
+ default:
+ return id == 1;
+ }
+}
+
+__weak void board_vddcore_init(u32 voltage_mv)
+{
+}
+
+/*
+ * gets OPP parameters (frequency in KHz and voltage in mV) from
+ * an OPP table subnode. Platform HW support capabilities are also checked.
+ * Returns 0 on success and a negative FDT error code on failure.
+ */
+static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
+ u32 *freq_khz, u32 *voltage_mv)
+{
+ u32 opp_hw;
+ u64 read_freq_64;
+ u32 read_voltage_32;
+
+ *freq_khz = 0;
+ *voltage_mv = 0;
+
+ opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
+ if (opp_hw)
+ if (!stm32mp1_supports_opp(opp_hw, cpu_type))
+ return -FDT_ERR_BADVALUE;
+
+ read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
+ 1000ULL;
+ read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
+ 1000U;
+
+ if (!read_voltage_32 || !read_freq_64)
+ return -FDT_ERR_NOTFOUND;
+
+ /* Frequency value expressed in KHz must fit on 32 bits */
+ if (read_freq_64 > U32_MAX)
+ return -FDT_ERR_BADVALUE;
+
+ /* Millivolt value must fit on 16 bits */
+ if (read_voltage_32 > U16_MAX)
+ return -FDT_ERR_BADVALUE;
+
+ *freq_khz = (u32)read_freq_64;
+ *voltage_mv = read_voltage_32;
+
+ return 0;
+}
+
+/*
+ * parses OPP table in DT and finds the parameters for the
+ * highest frequency supported by the HW platform.
+ * Returns 0 on success and a negative FDT error code on failure.
+ */
+int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
+{
+ ofnode node, subnode;
+ int ret;
+ u32 freq = 0U, voltage = 0U;
+ u32 cpu_type = get_cpu_type();
+
+ node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
+ if (!ofnode_valid(node))
+ return -FDT_ERR_NOTFOUND;
+
+ ofnode_for_each_subnode(subnode, node) {
+ unsigned int read_freq;
+ unsigned int read_voltage;
+
+ ret = stm32mp1_get_opp(cpu_type, subnode,
+ &read_freq, &read_voltage);
+ if (ret)
+ continue;
+
+ if (read_freq > freq) {
+ freq = read_freq;
+ voltage = read_voltage;
+ }
+ }
+
+ if (!freq || !voltage)
+ return -FDT_ERR_NOTFOUND;
+
+ *freq_hz = (u64)1000U * freq;
+ board_vddcore_init(voltage);
+
+ return 0;
+}
+
+static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
+ u32 *pllcfg, u32 *fracv)
+{
+ u32 post_divm;
+ u32 input_freq;
+ u64 output_freq;
+ u64 freq;
+ u64 vco;
+ u32 divm, divn, divp, frac;
+ int i, ret;
+ u32 diff;
+ u32 best_diff = U32_MAX;
+
+ /* PLL1 is 1600 */
+ const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
+ const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
+ const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
+
+ ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
+ if (ret) {
+ log_debug("PLL1 OPP configuration not found (%d).\n", ret);
+ return ret;
+ }
+
+ switch (clksrc) {
+ case CLK_PLL12_HSI:
+ input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case CLK_PLL12_HSE:
+ input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ default:
+ return -EINTR;
+ }
+
+ /* Following parameters have always the same value */
+ pllcfg[PLLCFG_Q] = 0;
+ pllcfg[PLLCFG_R] = 0;
+ pllcfg[PLLCFG_O] = PQR(1, 0, 0);
+
+ for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
+ post_divm = (u32)(input_freq / (divm + 1));
+ if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
+ continue;
+
+ for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
+ freq = output_freq * (divm + 1) * (divp + 1);
+ divn = (u32)((freq / input_freq) - 1);
+ if (divn < DIVN_MIN || divn > DIVN_MAX)
+ continue;
+
+ frac = (u32)(((freq * FRAC_MAX) / input_freq) -
+ ((divn + 1) * FRAC_MAX));
+ /* 2 loops to refine the fractional part */
+ for (i = 2; i != 0; i--) {
+ if (frac > FRAC_MAX)
+ break;
+
+ vco = (post_divm * (divn + 1)) +
+ ((post_divm * (u64)frac) /
+ FRAC_MAX);
+ if (vco < (PLL1600_VCO_MIN / 2) ||
+ vco > (PLL1600_VCO_MAX / 2)) {
+ frac++;
+ continue;
+ }
+ freq = vco / (divp + 1);
+ if (output_freq < freq)
+ diff = (u32)(freq - output_freq);
+ else
+ diff = (u32)(output_freq - freq);
+ if (diff < best_diff) {
+ pllcfg[PLLCFG_M] = divm;
+ pllcfg[PLLCFG_N] = divn;
+ pllcfg[PLLCFG_P] = divp;
+ *fracv = frac;
+
+ if (diff == 0)
+ return 0;
+
+ best_diff = diff;
+ }
+ frac++;
+ }
+ }
+ }
+
+ if (best_diff == U32_MAX)
+ return -1;
+
+ return 0;
+}
+
static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
u32 mask_on)
{
TIMEOUT_1S);
if (ret)
- pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
- mask_rdy, address, enable, readl(address));
+ log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
+ mask_rdy, address, enable, readl(address));
return ret;
}
static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
- int lsedrv)
+ u32 lsedrv)
{
u32 value;
val & RCC_OCRDYR_HSIDIVRDY,
TIMEOUT_200MS);
if (ret)
- pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
- address, readl(address));
+ log_err("HSIDIV failed @ 0x%x: 0x%x\n",
+ address, readl(address));
return ret;
}
break;
if (hsidiv == 4) {
- pr_err("clk-hsi frequency invalid");
+ log_err("clk-hsi frequency invalid");
return -1;
}
TIMEOUT_200MS);
if (ret) {
- pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
- pll_id, pllxcr, readl(pllxcr));
+ log_err("PLL%d start failed @ 0x%x: 0x%x\n",
+ pll_id, pllxcr, readl(pllxcr));
return ret;
}
if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
- debug("invalid refclk = %x\n", (u32)refclk);
+ log_err("invalid refclk = %x\n", (u32)refclk);
return -EINVAL;
}
if (type == PLL_800 && refclk >= 8000000)
setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
}
+static __maybe_unused int pll_set_rate(struct udevice *dev,
+ int pll_id,
+ int div_id,
+ unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ unsigned int pllcfg[PLLCFG_NB];
+ ofnode plloff;
+ char name[12];
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ enum stm32mp1_plltype type = pll[pll_id].plltype;
+ int divm, divn, divy;
+ int ret;
+ ulong fck_ref;
+ u32 fracv;
+ u64 value;
+
+ if (div_id > _DIV_NB)
+ return -EINVAL;
+
+ sprintf(name, "st,pll@%d", pll_id);
+ plloff = dev_read_subnode(dev, name);
+ if (!ofnode_valid(plloff))
+ return -FDT_ERR_NOTFOUND;
+
+ ret = ofnode_read_u32_array(plloff, "cfg",
+ pllcfg, PLLCFG_NB);
+ if (ret < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ fck_ref = pll_get_fref_ck(priv, pll_id);
+
+ divm = pllcfg[PLLCFG_M];
+ /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
+ divy = pllcfg[PLLCFG_P + div_id];
+
+ /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
+ * So same final result than PLL2 et 4
+ * with FRACV
+ * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
+ * / (DIVy + 1) * (DIVM + 1)
+ * value = (DIVN + 1) * 2^13 + FRACV / 2^13
+ * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
+ */
+ value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
+ value = lldiv(value, fck_ref);
+
+ divn = (value >> 13) - 1;
+ if (divn < DIVN_MIN ||
+ divn > stm32mp1_pll[type].divn_max) {
+ dev_err(dev, "divn invalid = %d", divn);
+ return -EINVAL;
+ }
+ fracv = value - ((divn + 1) << 13);
+ pllcfg[PLLCFG_N] = divn;
+
+ /* reconfigure PLL */
+ pll_stop(priv, pll_id);
+ pll_config(priv, pll_id, pllcfg, fracv);
+ pll_start(priv, pll_id);
+ pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
+
+ return 0;
+}
+
static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
{
u32 address = priv->base + (clksrc >> 4);
ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
TIMEOUT_200MS);
if (ret)
- pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
- clksrc, address, readl(address));
+ log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
+ clksrc, address, readl(address));
return ret;
}
u32 stgenc, cntfid0;
ulong rate;
- stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
-
+ stgenc = STM32_STGEN_BASE;
cntfid0 = readl(stgenc + STGENC_CNTFID0);
p = stm32mp1_clk_get_parent(priv, STGEN_K);
rate = stm32mp1_clk_get(priv, p);
if (cntfid0 != rate) {
u64 counter;
- pr_debug("System Generic Counter (STGEN) update\n");
+ log_debug("System Generic Counter (STGEN) update\n");
clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
counter = (u64)readl(stgenc + STGENC_CNTCVL);
counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
/* need to update gd->arch.timer_rate_hz with new frequency */
timer_init();
- pr_debug("gd->arch.timer_rate_hz = %x\n",
- (u32)gd->arch.timer_rate_hz);
- pr_debug("Tick = %x\n", (u32)(get_ticks()));
}
}
ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
TIMEOUT_200MS);
if (ret)
- pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
- clkdiv, address, readl(address));
+ log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
+ clkdiv, address, readl(address));
return ret;
}
unsigned int clksrc[CLKSRC_NB];
unsigned int clkdiv[CLKDIV_NB];
unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
- ofnode plloff[_PLL_NB];
+ unsigned int pllfracv[_PLL_NB];
+ unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
+ bool pllcfg_valid[_PLL_NB];
+ bool pllcsg_set[_PLL_NB];
int ret;
int i, len;
int lse_css = 0;
/* check mandatory field */
ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
if (ret < 0) {
- debug("field st,clksrc invalid: error %d\n", ret);
+ dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
if (ret < 0) {
- debug("field st,clkdiv invalid: error %d\n", ret);
+ dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
/* check mandatory field in each pll */
for (i = 0; i < _PLL_NB; i++) {
char name[12];
+ ofnode node;
sprintf(name, "st,pll@%d", i);
- plloff[i] = dev_read_subnode(dev, name);
- if (!ofnode_valid(plloff[i]))
- continue;
- ret = ofnode_read_u32_array(plloff[i], "cfg",
- pllcfg[i], PLLCFG_NB);
- if (ret < 0) {
- debug("field cfg invalid: error %d\n", ret);
- return -FDT_ERR_NOTFOUND;
+ node = dev_read_subnode(dev, name);
+ pllcfg_valid[i] = ofnode_valid(node);
+ pllcsg_set[i] = false;
+ if (pllcfg_valid[i]) {
+ dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
+ ret = ofnode_read_u32_array(node, "cfg",
+ pllcfg[i], PLLCFG_NB);
+ if (ret < 0) {
+ dev_dbg(dev, "field cfg invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+ pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
+
+ ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
+ PLLCSG_NB);
+ if (!ret) {
+ pllcsg_set[i] = true;
+ } else if (ret != -FDT_ERR_NOTFOUND) {
+ dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
+ i, ret);
+ return ret;
+ }
+ } else if (i == _PLL1) {
+ /* use OPP for PLL1 for A7 CPU */
+ dev_dbg(dev, "DT for PLL %d with OPP\n", i);
+ ret = stm32mp1_pll1_opp(priv,
+ clksrc[CLKSRC_PLL12],
+ pllcfg[i],
+ &pllfracv[i]);
+ if (ret) {
+ dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
+ return ret;
+ }
+ pllcfg_valid[i] = true;
}
}
- debug("configuration MCO\n");
+ dev_dbg(dev, "configuration MCO\n");
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
- debug("switch ON osillator\n");
+ dev_dbg(dev, "switch ON osillator\n");
/*
* switch ON oscillator found in device-tree,
* HSI already ON after bootrom
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass, digbyp, lsedrv;
+ int bypass, digbyp;
+ u32 lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
stm32mp1_csi_set(rcc, 1);
/* come back to HSI */
- debug("come back to HSI\n");
+ dev_dbg(dev, "come back to HSI\n");
set_clksrc(priv, CLK_MPU_HSI);
set_clksrc(priv, CLK_AXI_HSI);
set_clksrc(priv, CLK_MCU_HSI);
- debug("pll stop\n");
+ dev_dbg(dev, "pll stop\n");
for (i = 0; i < _PLL_NB; i++)
pll_stop(priv, i);
/* configure HSIDIV */
- debug("configure HSIDIV\n");
+ dev_dbg(dev, "configure HSIDIV\n");
if (priv->osc[_HSI]) {
stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
stgen_config(priv);
}
/* select DIV */
- debug("select DIV\n");
+ dev_dbg(dev, "select DIV\n");
/* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
/* configure PLLs source */
- debug("configure PLLs source\n");
+ dev_dbg(dev, "configure PLLs source\n");
set_clksrc(priv, clksrc[CLKSRC_PLL12]);
set_clksrc(priv, clksrc[CLKSRC_PLL3]);
set_clksrc(priv, clksrc[CLKSRC_PLL4]);
/* configure and start PLLs */
- debug("configure PLLs\n");
+ dev_dbg(dev, "configure PLLs\n");
for (i = 0; i < _PLL_NB; i++) {
- u32 fracv;
- u32 csg[PLLCSG_NB];
-
- debug("configure PLL %d @ %d\n", i,
- ofnode_to_offset(plloff[i]));
- if (!ofnode_valid(plloff[i]))
+ if (!pllcfg_valid[i])
continue;
-
- fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
- pll_config(priv, i, pllcfg[i], fracv);
- ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
- if (!ret) {
- pll_csg(priv, i, csg);
- } else if (ret != -FDT_ERR_NOTFOUND) {
- debug("invalid csg node for pll@%d res=%d\n", i, ret);
- return ret;
- }
+ dev_dbg(dev, "configure PLL %d\n", i);
+ pll_config(priv, i, pllcfg[i], pllfracv[i]);
+ if (pllcsg_set[i])
+ pll_csg(priv, i, pllcsg[i]);
pll_start(priv, i);
}
/* wait and start PLLs ouptut when ready */
for (i = 0; i < _PLL_NB; i++) {
- if (!ofnode_valid(plloff[i]))
+ if (!pllcfg_valid[i])
continue;
- debug("output PLL %d\n", i);
+ dev_dbg(dev, "output PLL %d\n", i);
pll_output(priv, i, pllcfg[i][PLLCFG_O]);
}
stm32mp1_lse_wait(rcc);
/* configure with expected clock source */
- debug("CLKSRC\n");
+ dev_dbg(dev, "CLKSRC\n");
set_clksrc(priv, clksrc[CLKSRC_MPU]);
set_clksrc(priv, clksrc[CLKSRC_AXI]);
set_clksrc(priv, clksrc[CLKSRC_MCU]);
set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
/* configure PKCK */
- debug("PKCK\n");
+ dev_dbg(dev, "PKCK\n");
pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
if (pkcs_cell) {
bool ckper_disabled = false;
/* STGEN clock source can change with CLK_STGEN_XXX */
stgen_config(priv);
- debug("oscillator off\n");
+ dev_dbg(dev, "oscillator off\n");
/* switch OFF HSI if not found in device-tree */
if (!priv->osc[_HSI])
stm32mp1_hsi_set(rcc, 0);
if (div > 128)
div = 128;
- debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
/* stop the requested output */
clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
/* change divider */
int p;
switch (clk->id) {
+#if defined(STM32MP1_CLOCK_TREE_INIT) && \
+ defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
+ case DDRPHYC:
+ break;
+#endif
case LTDC_PX:
case DSI_PX:
break;
default:
- pr_err("not supported");
+ dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
return -EINVAL;
}
p = stm32mp1_clk_get_parent(priv, clk->id);
+ dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
if (p < 0)
return -EINVAL;
switch (p) {
+#if defined(STM32MP1_CLOCK_TREE_INIT) && \
+ defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
+ case _PLL2_R: /* DDRPHYC */
+ {
+ /* only for change DDR clock in interactive mode */
+ ulong result;
+
+ set_clksrc(priv, CLK_AXI_HSI);
+ result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
+ set_clksrc(priv, CLK_AXI_PLL2P);
+ return result;
+ }
+#endif
+
case _PLL4_Q:
/* for LTDC_PX and DSI_PX case */
return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
clk.id = 0;
if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
if (clk_request(dev, &clk))
- pr_err("%s request", name);
+ log_err("%s request", name);
else
priv->osc[index] = clk_get_rate(&clk);
}
for (i = 0; i < NB_OSC; i++) {
stm32mp1_osc_clk_init(name[i], priv, i);
- debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
+ dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
}
}
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_GET_DRIVER(stm32mp1_clock),
+ DM_DRIVER_GET(stm32mp1_clock),
&dev);
if (ret)
return ret;
/* clock tree init is done only one time, before relocation */
if (!(gd->flags & GD_FLG_RELOC))
result = stm32mp1_clktree(dev);
+ if (result)
+ dev_err(dev, "clock tree initialization failed (%d)\n", result);
#endif
#ifndef CONFIG_SPL_BUILD
-#if defined(DEBUG)
+#if defined(VERBOSE_DEBUG)
/* display debug information for probe after relocation */
if (gd->flags & GD_FLG_RELOC)
stm32mp1_clk_dump(priv);
#endif
+ gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
+ gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
+ /* DDRPHYC father */
+ gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
#if defined(CONFIG_DISPLAY_CPUINFO)
if (gd->flags & GD_FLG_RELOC) {
char buf[32];
- printf("Clocks:\n");
- printf("- MPU : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
- printf("- MCU : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
- printf("- AXI : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
- printf("- PER : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
- /* DDRPHYC father */
- printf("- DDR : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
+ log_info("Clocks:\n");
+ log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
+ log_info("- MCU : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
+ log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
+ log_info("- PER : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
+ log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#endif
.name = "stm32mp1_clk",
.id = UCLASS_CLK,
.ops = &stm32mp1_clk_ops,
- .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
+ .priv_auto = sizeof(struct stm32mp1_clk_priv),
.probe = stm32mp1_clk_probe,
};
projects / platform / kernel / u-boot.git / blobdiff